Cascaded diode clamped inverter based grid-connected photovoltaic energy conversion system with enhanced power handling capability and efﬁciency

This paper proposes a high power factor converter based symmetrical topology entitled cascaded diode clamped half-bridge multi-level inverter for high voltage photovoltaic (PV) applications along with a hybrid multi-level pulse width modulation technique. Due to the restriction of peak inverse voltage (PIV) on switching devices, the PV array voltage is restricted. Also, operating at high current causes switching losses and degrades the efﬁciency, hence limiting its power enhancement. Unbalance in the capacitor voltages leads to high PIV across the devices, which is undesirable. The proposed topology allows connecting double times PV array voltage keeping the PIV and current alike cascaded H-bridge multi-level inverter, hence increasing the efﬁciency, and thereby reducing cost and space. It ensures a capacity enhancement in renewable energy systems linked to on/off-grid applications. The projected scheme allows even power distribution among the sources along with maximum and efﬁcient energy conversion. The control scheme adopted has the ability to balance dc-link capacitor voltage in each half-bridge results in equal PIV and switching losses across all the devices. Simulations of PV connected modiﬁed topology is carried out and validated with experimental results.


INTRODUCTION
For high-voltage (HV) grid integrated operations, the conventional two-level power converters require either a step-up transformer or HV semiconductor devices [1]. The multi-level inverter (MLI) structure has been introduced as an alternative in high-power and high/medium-voltage renewable applications. This multi-level approach for dc to ac conversion offers many advantages, as reported in [2]. MLIs are classified based on the magnitude of their dc supply voltage sources. Symmetric converters have equal dc supply voltage sources. Regular converters like diode clamped [3], cascaded H-bridge (CHB) [4], and flying capacitor [5] MLIs are symmetric. Asymmetric converters require different amplitudes of dc voltage sources, which increases the dc-dc converter cost, uneven power distribution among the sources, and smaller modularity. Hence, symmetric converters are preferred over asymmetric converters for HV photovoltaic (PV) applications. To reduce the number of Hinago and Koizumi [7,8] proposed "switched series/parallel sources (SSPS)-based MLI." It could not synthesize zero level voltage; hence, H-bridge cannot be operated at switching frequency. "Series-connected switched sources (SCSS)-based MLI," has been reported in [9]. Babaei [10] presented "multilevel module (MLM)-based MLI." Both topologies were unable to distribute even power among the sources, and the devices undergo different PIV stress, which increases the switching and conduction losses. Babaei [11] also proposed, "Cascaded multilevel inverter using sub-multilevel cells" (CSMC). Though it has low conduction losses, it is not able to synthesize zero level voltage, and hence H-bridge cannot be operated at switching frequency. It fails to distribute even power from the sources. In [12], Najafi proposed reverse voltage (RV) topology in which even power distribution among the sources is not possible, and conduction and switching losses for the switches may not be the same. However, topologies with separate level-generation and polarity parts may find restrictions for high-voltage applications because of complex switching, and the devices in the polarity-generation part need to block the total operating voltage.
Coming to the RDC without H-bridge topologies, Ceglia et al. [13][14][15] reported "T-type inverter," in which even power distribution among the sources is not possible and different devices undergo different PIV, due to which different switching frequency (high PIV devices with low switching frequency and low PIV devices with high switching frequency) need to be maintained to overcome the switching losses. Babaei et al. [16] introduced "cascaded bipolar switched cells (CBSC)-based MLI," which again suffers from uneven power distribution among the sources, and it requires bidirectional switches. The applications, comparison, and limitations of these topologies have been given in [17][18][19][20]. From the above literature, it can be concluded that RDC converters are not reliable for HV PV applications. Conventional converters for renewable applications and their modulation techniques are presented in [21]. As isolated dc supplies are readily available in a PV system, among the regular converters, CHB MLI is preferred in renewable applications [22] due to its modular structure, fewer devices, symmetry in structure, high-reliability, and fault-tolerant capability in medium and high voltage applications. Figure 4 displays an m-level traditional CHB MLI circuit diagram consisting of "h" number of H-Bridge cascaded cells. Each PV array voltage is connected to a dc-dc converter to extract maximum power from the PV array using the perturb and observe algorithm, and the output of the converter is fed to H-bridge cell, as shown in Figure 4. The number of voltage levels (m) in each phase voltage is given The pulse width modulation (PWM) technique used is phaseshifted multi-carrier modulation. Each cell input dc voltage, V dczh is given as where, z stands for phases {a, b, c} and h for cell number.
To inject more power into the grid, an HV PV array is required. Series connected HV PV array ensures high conversion efficiency [23], but the device voltage stress on switches limits high voltage input to individual H-bridge in CHB MLI. A modified cascaded diode clamped half-bridge (CDCHB) inverter is presented in [24] to enhance power capability double times and also improve the overall power rating. This paper is an extension of the same with HV PV application addressing the dc-link capacitor voltage balance in each half-bridge (HB).
In this reading, in simulation and experimentation for threephase 415 V (rms) grid, a dc-link voltage of 300 and 600 V is retained for CHB and CDCHB MLI, respectively. To extend for other drives and renewable applications, a mathematical model is presented for the proposed converter in Section 3. The control strategy to improve power quality and each cell dc-link capacitor voltage balance is discussed in Section 4. Both the level-shift and phase-shift pulse width modulation (PWM) technique is used in Section 5. Quality evaluation, simulation, and experimental results of the proposed topology are discussed in Section 6.

PROPOSED TOPOLOGY
In the proposed topology, a three-level diode clamped functions as a half-bridge cell that can produce three different output voltage levels and is cascaded to form a m-level MLI, as depicted in Figure 5. Henceforward, it can be called as cascaded diode clamped half-bridge (CDCHB) MLI. The two capacitors connected in each half-bridge acts as two single dc sources. Proposed topology allows the user to connect two PV arrays (which were connected to a dc-dc converter to extract maximum power from PV array) rather than connecting only one PV array system as in CHB MLI. It means that CDCHB MLI's applied voltage is twice the voltage applied to the CHB MLI, resulting in an increased power management capacity on the dc side of the MLI's. It is accomplished by certain modifications in CHB MLI networks without any changes in switch count. Therefore, it can provide support without additional cost or space to the standing topologies (with modular structure). PIV is directly proportional to the switching losses, as the total applied dc cell voltage is divided into two halves, PIV is reduced. As in the case of CHB MLI, the PIV across the device is the same. For "h" number of half-bridges in each cell (HBs), the voltage levels (m) in each phase of CDCHB are alike as in (1). Every cell voltage and the current value is 2V dczh and I dczh , respectively where, "z" represents phases {a, b, c}.V dczh is condenser voltage and, k = 1, 2 (1 = upper cell, and 2 = lower cell). Count of cell voltages At the output, the resultant phase and line voltage levels in both CHB and CDCHB MLIs are equal. Additional power capability at the input dc side in the proposed converter permits enhanced power injection into the grid to fulfill further load requirements.

MATHEMATICAL MODEL OF CHBDC MLI
The CDCHB MLI shown in Figure 5 comprises power switches T z1 , T z2 , T ′ z1 and T ′ z2 in the first cell such that T ′ z1 and T ′ z2 are complementary switches of T z1 and T z2 , respectively. If a switch switches on (or off) as 1 (or 0), then to prevent short-circuit, the relationship between any switch and its complimentary switch can be written mathematically as where, y = 1, 2, … (m − 1). Likewise, it also establishes the same restriction for the remaining cell. Condensers share the dc-link voltage equally in every cell. It is assumed that an isolated identical dc source supplies to the dc-link voltage in each cell. Let d z be the switching function specifying the value of per unit phase voltage, that is, d z = 1, 1∕2, 0, −1∕2, −1 if V dczhk is the corresponding output voltage. It can be accomplished by maintaining   Table 1. The corresponding modes of operation for two cascaded HBs can be observed in Figure 6. The generalized mathematical function of d z is given as Algebraic summation of each HB voltage gives the variance in output ac side phase voltage. The upper and lower HB voltages (V z1 and V z2 , respectively) of the ac side switch with the positive, negative, and zero voltage of the corresponding dc-link capacitor voltages. As a function of the dc-link capacitor voltage, the output phase voltage, v z can be generalized as in (6). where, for every HB k = 1 and 2 for the upper and lower capacitor, respectively. To estimate the intermittent value, Newton's forward interpolation is applied in (6). A generalized fourth-order polynomial for v z is obtained as in "(see (7))". Equation (7) can be reduced to (8).
The control scheme of CDCHB MLI With the generalized phase voltage of (10), the voltages of the line can be described in (11), (12), and (13).
The voltages of the phase can be described in (14), (15), and (16). where

CONTROL STRATEGY
In the proposed topology, "One proportional-integral (PI) controller for the overall voltage, one for a dc bus, and one proportional controller for the current," control scheme presented in [25] has been adopted with considerable modification to balance individual capacitor voltages and is shown in Figure 7. The objectives of the control scheme are: i. Balancing individual dc-link capacitor voltages.
ii. Sinusoidal ac current injection into the grid, which attains unity power factor (UPF).
iii. Maximum power extraction from PV and injecting the same into the grid.
The control scheme is divided into two parts, namely primary and secondary parts. Primary part consists of a voltage controller (PI) to maintain the sum of all cells dc-link voltage (2V dcz1 + 2V dcz2 + ⋯ + 2V dczh ) through the choice of the amplitude of the grid current (i z ), maximum power point tracking (MPPT) algorithm for maximum power extraction, a reference dc current generator (I dc(gen) ), and current controller. The sum of all modulating signals (p z1 + p z2 + ⋯ + p zh ) is obtained from the primary part. To control remaining (h − 1) HBs and to obtain a modulation signal of primary HB, a secondary part is featured. The secondary part consists of a voltage controller to maintain a corresponding capacitor dc-link voltage. It directly results in a corresponding cell switching function (p * z2 , p * z3 , … , p * zh ).

Primary part
Sum of the actual dc voltages of all HBs are compared with the reference dc voltage (hV * dc ), and the error (ΔV dc ) is given to the PI1 (total voltage controller) resulting in reference current component (I * dc ) which balances the capacitor voltages to their reference value through the choice of grid current.
By converting (17) from s-domain to time-domain, we get, where, k p1 and k i1 are proportional and integral constant in the PI1 controller. As the power generated from PV is entirely dependent on environmental conditions, it is essential to estimate the amount of power extracted at all times. MPPT is used to extract maximum power from the individual array, and corresponding individual dc current component (I dc hk ) is obtained. Sum of these individual components results in total current dc component (I dc(gen) ), which is a variable with respect to the environmental condition and mathematically given as, Therefore, the power fed to the converter after considering the power required to maintain the capacitor voltages to the reference value is given as, Substituting (18) and (20) in (21) ΔI The error current ΔI dc obtained from (22) is a dc component and source current is an ac component. To synchronize and preserve UPF, respective phase voltage unit template (v zu ) is obtained using PLL (phase-locked loop) and is multiplied to (22) resulting in reference ac current i * z is compared with actual ac side current (i z ) results Δ(i z ) Δi z is succeeded by current controller (P) giving rise to reference where, k p2 is the proportionality constant of P controller. Equation (26) has been used to design current controller, where v = v a − (V H1 + V H2 + ⋯ + V Hh ), L z and R are the coupling inductance and its resistance, respectively. Applying Laplace transform to (26) we get: The current control scheme is shown in Figure 8. Now, by considering respective phase sinusoidal reference signal v u (t ) = sin( .t ), = 2. .50rad ∕s, the output of controller is given as: is the closedloop transfer function of the controller, and I * z (s) is considered as a sinusoidal signal then Laplace of it is s 2 + 2

FIGURE 11
Cascaded dc/ac inverter Substituting the values T s = 1∕100000s, L z = 12mH, R = 0.31Ω and k p2 = 2000, the stability of the controller can be observed from the bode plot in Figure 9. The system stability of (29) is verified using SISOTOOL in MATLAB. If the reference signal is altered due to steady-state error and phase errors, the P controller can be replaced with the PR (proportional + resonant) controller. Normalization technique is used, where reference voltage (v * z ) value is subtracted from actual voltage, (v z ) and dividing it by hV * dc , resulting into sum of the switching functions (i.e. modulating signals), p z1 + p z2 + ⋯ + p zh .
The individual modulating signals (p z2 , p z3 , … , p zh ) derived directly from the secondary part is subtracted from this sum of the modulating signals. The dc-link capacitor voltage of primary HB (i.e. cell z1) is maintained at the reference voltage by this generated modulating signal. A voltage controller (PI3) is used to balance the upper and lower capacitor voltages, that is, V dczh1 and V dczh2 , respectively. The generated modulating signal (p z1 ) is subtracted from the output of PI3 controller to obtain the modulating signal p * z1 .

Secondary part
In this part, the control scheme of remaining (h − 1) HBs are featured. Every individual HB dc-link capacitor voltage is compared with the reference voltage (V * dc ), and the output is given to a voltage controller (PI2), giving rise to a corresponding reference dc current component where, k p3 and k i3 is proportionality and integral constant of the PI2 controller. To synchronize, the dc current component obtained in (31), v zu is multiplied. After normalizing the modulating signal, p z2 is obtained as in (32): The generated modulating signal is subtracted from the output of the PI4 controller to obtain the modulating signal p * zh . Where PI4 controller (voltage controller) is to balance the upper and lower capacitor voltages, that is, V dczh1 and V dczh2 , respectively. In the present work, five-level (m = 5) CDCHB is presented with h = 2, that is, two HBs are employed in each leg. Accordingly, the control scheme is presented in Figure 7.

SWITCHING STRATEGY
In the proposed topology, a hybrid PWM scheme is used to generate switching signals. Each HB is diode clamped, and hence, level-shifted triangular carriers are used. For the cascade HBs, phase-shifted triangular carriers are used. Since together level shift and phase shift carriers are utilized, this scheme is termed as a hybrid PWM scheme. Since the three phases are symmetric, here only phase-a is discussed . PWM technique for cell a1 and a2 and its switching pattern is shown in Figure 10. Two triangular signals c r1 and c r2 are evenly set apart in a positive and negative band, respectively for each cell, as in the diode clamped inverter. A phase interval of 360∕h is established among each carrier pair (c r3 and c r4 ) for successive cell(s), as shown in Figure 10. The modulating signal p * a1 has been compared with two level-shifted carriers c r1 and c r2 , resulting in switching signals for T a1 and T a2 along with their complementary signals for T ′ a1 1 and T ′ a2 , respectively, in cell-a1. Similarly, for cell-a2, the modulating signal p * a2 has been compared with two phase-shifted carriers c r3 and c r4 , resulting in switching signals for T a3 and T a4 along with their comple-mentary signals for T ′ a3 , and T ′ a4 , respectively, as presented in [26].

SIMULATION AND EXPERIMENTAL RESULTS
To validate the proposed converter, simulation and experimental tests are carried out. A CDCHB MLI converter prototype has been built in the laboratory. The parameters used for simulation and experiment are given in Table 2. The control signals to the converter have been generated by a dSPACE ds1202 controller. The devices used in experimentation are: AD202 isolation amplifier (voltage sensor), 1000 V; HTP25 Hall sensor (current sensor), 1000:1, ±25 A; 1:1 isolation transformer 415 V, 50 Hz; RC snubber circuit 100 Ω, 221 1kV ceramic capacitor; IGBT-1MBH15D-060, 600 V, 37A; clamping diode U1560; dc-link capacitor -PG -6TUPS 2200 F 450 V dc.
Due to advantages like better utilization per PV module, the ability to mix different sources, and redundancy of the system out of five different configurations of the PV system presented in [27], "cascaded dc/ac inverter," is preferred with a slight modification. A dc-dc converter has been connected between PV array and inverter, as shown in Figure 11. The separate dc links in the MLI make independent voltage control possible. As a result, individual MPPT control in each PV array can be achieved, and the energy harvested from PV panels can be maximized. ELDORA VSP.72.325.03.04 model PV panel is used with specifications, as shown in Table 3. Each PV array consists of four series and one parallel-connected PV panels and generates 1.3 kW power in simulation and experimentation.

6.1
Simulation results Figure 12 shows that simulated CHB and CDCHB MLI phase to neutral voltage (v a ) and current (i a ) waveforms for phase-"a" under steady-state condition is in phase with a power factor of 0.998 and 0.995, respectively. The rms current (i a ) injected into the grid in CHB, and CDCHB MLI is 11.7 A and 21.9 A with a THD of 2.65% and 4.44%, respectively, as shown in Figure 13. From Figure 14, the power which implies the even power distribution of individual cell. The power generated from the PV depends upon the climatic conditions. To observe the robustness of the MLI to the climatic changes, an irradiation change from 1000 to 800 W∕m 2 is applied at time = 4s. From Figure 15, the three-phase injected grid currents are well balanced for the corresponding irradiation change. It can be observed from Figure 16 that the dc-link capacitor voltage of each capacitor in both the converters are well balanced and maintained at 300 V even after the irradiation change. The dc-dc converter input and output voltages are 150 (nearly) and 300 V, respectively as presented in Figure 17 for both the converters. Phase voltage of three-phases has been presented in Figure 18, which depicts the five-level operation of both the converters and hence confirmed that the converter is symmetric in nature. PIV is directly proportional to switching losses, in spite of applying a double voltage across the proposed converter, from Figure 19, the PIV across each device is the same as that of the CHB MLI, that is, 300 V affirms the decrease of switching losses as well as even loss distribution. Figure 20 presents the inverter efficiency at different input power levels. The inverter efficiency can be calculated as output The efficiency in all the measurements is above 90%, which is more than the CHB presented in [28], that is, 86.8%. Figure 21 gives a comparison of the proposed converter with conventional   where V PIV is the voltage blocked by a switch, 'I ' is the device current, t on and t o f f are the on and off times of switch, respectively, and f s is the switching frequency. It may be noted that the PIV across the proposed converter is almost 50% of the applied cell voltage.

Experimental results
To validate the proposed topology with the simulation results, a three-phase five-level CDCHB MLI converter has been built in the laboratory. Fig. 22 shows the experimental solar panel and the CDCHB MLI converter. The dc-link of each cell is maintained at 600V, that is, each capacitor voltage is maintained at 300 V. The experimental results are presented in Figure 23. Figure 23(a) shows the phase to neutral voltage (v a ) and three-phase currents (i a , i b , i c ,) waveforms for phase-"a" are in phase. Figure 23(a) also depicts the balanced injected three-phase currents into the grid. The THD of the injected current (i a ) in the grid is 3.8%, as shown in Figure 23(b), which is near to the simulated one. Dc-dc converter input voltage (v pva1 ) and current (i pva1 ) that is, nothing but the four series-connected PV panels current is shown in Figure 23(c). The dc-dc converter input voltage is 150 V (nearly) and the output voltage is 300 V as presented in Figures 23(c) and 23(d), respectively. The dc-link capacitor voltages in phase-"a" shown in Figure 23(d) are fairly balanced and maintained at voltage 300 V. From Figure 23(e), five-level operation of the proposed converter can be observed, and each level is maintained at 300 V. From Figure 23(f), it can be observed that the PIV across each device is 300 V, which is half of the applied cell voltage (=600 V).

Observation and discussion
A comparison table of simulation results of CHB and CDCHB MLI and experimental CDCHB MLI is mentioned in Table 4.
From Figure 12, it can be observed that the current injection into the grid in CDCHB MLI is double (21.9 A) when compared with the conventional CHB MLI (11.7 A) by maintaining the PIV across each device as constant. The CDCHB MLI grid power is increased twice as much as the CHB MLI power. In both the converters, the voltage and current are in phase by maintaining an almost unity power factor. Figure 18 shows the successful five-level operation in both the converters and each level is maintained at 300V. Further, it can be observed from Figure 19 that PIV in the proposed CDCHB is 50% of the applied cell voltage. A good agreement has been found between the experimental results in Figure 23 of CDCHB MLI and the simulation results.

Novelty and advantages of CDCHB MLI
As the PIV increases the converter efficiency decreases, the power enhancement by increasing input voltage is therefore limited in CHB MLI. Uneven device stress (as discussed in RDC) may also lead to decay in inverter efficiency. The proposed converter allows us to connect double the voltage that of CHB MLI without increasing the stress across the devices and also preserve even PIV. Due to symmetry in nature and adopted control scheme, the inverter can distribute even power from all the cells. Different ratings of switches may increase the principle cost of the converter, whereas, in the present inverter, the rating of all the devices is the same permits modular in structure and principle cost, and maintenance is less. Since all the devices are operated at the same switching frequency, the switching losses are distributed evenly. Further, the detailed advantages of the proposed converter over other topologies are presented in Table 5.

CONCLUSION
An enhanced power interfacing converter (CDCHB MLI) for the connection of HV PV to the utility grid has been presented. The performance of the proposed converter in steady-state operation has been verified through simulation and experimentation using a prototype. This model provides excellent power qualities like negligible source current THD, maintaining nearly unity power factor at the source side, well dc-link capacitor balance, and reduced output dc voltage ripple. It effectively improves the power rating, eases PIV, and reduces cost, space, and switching losses. Due to advantages like segmental architecture, equivalent device stress, and uniform power-sharing, it can be used in HV drives and renewable applications.