A full sequence impedance modelling and stability analysis of the virtual synchronous generator with inner loops

Virtual synchronous generator (VSG) has been widely studied owing to its inertia support to the grid. However, the stability of VSG is not analysed accurately for actual applica-tions in previous studies that overlook voltage and current inner loops of VSG. Since inner loops are essential to control output voltage and current accurately in practical engineering, this study focuses on stability analysis of the interconnection system of VSG and the grid by sequence impedance modelling of VSG with inner loops. The complete sequence impedance model for VSG with inner loops is built and compared with that of the VSG-ignoring inner loops, and then the stability is analysed based on that. It shows that inner loops bring the risk of instability and oscillation for VSG, which was not predicted in previous studies. Then, the inﬂuence of each parameter of inner loops on the impedance and oscillation is analysed, showing that the oscillation can hardly be eliminated by tuning the parameters of inner loops. Therefore, corresponding virtual resistor with proper value is studied and adopted in VSG with inner loops to avoid oscillation. Finally, the correctness of theoretical analysis and the effectiveness of the adopted virtual resistance are veriﬁed by the hardware-in-the-loop experiments.


INTRODUCTION
The high penetration of distributed energy resources (DERs) gives rise to the extensive use of inverters that is necessary for the DERs to interface to power grid. Originally, these inverters are controlled for maximum power output of the DERs and do not participate in grid support [1]. Consequently, the inertia and the regulation capability of grid frequency decrease along with the high penetration of DERs, which is hazardous to the stationary of grid frequency and may even cause some units splitting from the grid due to sharp fluctuation of frequency under the disturbance of loads [2][3][4]. In order to ensure sufficient inertia and the modulation ability of grid frequency under high penetration, inverters of DERs are required to provide inertia support to the grid and take part in the frequency regulation as traditional synchronous generators (SGs) [4]. Among a variety of control schemes of inverters proposed to participate in the frequency regulation of grid, one of the representative control schemes is virtual SGs (VSGs) [5]. VSG is a control scheme that emulates the fundamental swing equation and the primary regulation of voltage and frequency of SG in order to provide voltage and frequency support for the grid. Thus, VSG has become a focus of research in recent years [6][7][8].
However, the stability analysis of VSG-controlled inverter connected to the grid has not been analysed thoroughly in existing literatures. When it comes to stability analysis of inverters connected to the grid, there are two dominating approaches: State-space model [9,10] and impedance model methods [11]. The state-space model method lacks agility for modelling since it requires all the parameters before building and if some details of control schemes change, the model must be rebuilt. Besides, the state-space modelling process is rather sophisticated [10]. Impedance modelling method is less complicated and the Nyquist criterion for the impedance modelling makes stability analysis more intuitive [12]. Therefore, impedance modelling has been used broadly to analyse the stability problem of inverters connected to the grid [13].
The two prevailing methods for impedance modelling are DQ-frame impedance modelling [14][15][16] and sequence impedance modelling [17][18][19][20][21][22][23]. The classical method, DQ-frame modelling is easier for model building, but it is hard to test and verify in practice, and its stability criteria often involve massive calculation. On the other hand, sequence impedance modelling, which is first proposed in [24], has clearer physical meaning by obtaining positive and negative-sequence impedance individually. Furthermore, by applying the Nyquist criterion [25], the stability problem can be directly visualised with corresponding diagram [26]. On the basis of the above considerations, sequence impedance modelling is adopted in this study.
Sun [24] first proposed the harmonic linearisation method and demonstrated the sequence impedance model of a basic rectifier that opened the perspective of sequence impedance when studying stability of power-electronic devices. In [27], the sequence impedance models for voltage and current doubleclosed loops themselves are built, but it does not show what the impedance will be if the outer-power loop of VSG is added to the control strategies. Although some studies have been carried out on impedance modelling for VSG, they are deficient and incomplete in practical aspects [14,22]. In [14], impedance model of VSG is built in DQ frame but how the inner loops influence the output impedance is not demonstrated. The authors in [20] built the sequence impedance models for VSGs with different control schemes and compared their characteristics, but they did not consider the inner loops of VSGs fully. In [22], the authors propose the impedance model for VSG and compare it with traditional current-control scheme but overlook the inner loops when building the VSG-impedance model, then point out that VSG does not have the risk of instability that cannot reflect the actual situations where the inner loops are implanted.
Nevertheless, in industrial applications, the inner loops are necessary for achieving fast and accurate voltage and current control [28], so it is very meaningful to analyse how the inner loops can affect the output impedance and the stability of VSGs connected to the grid. In this study, taking into consideration of the inner loops, a full and complete sequence impedance model for VSG is built in Section 2, which shows that the inner loops can bring in capacitive factors into impedance. In Section 3, the stability of VSG connected to the grid is analysed to show that the inner loops bring risk of instability. Then, each parameter of the inner loops is studied to reveal how each one affects the impedance of VSG and system stability. In addition, the suggestion that virtual resistance is needed for the control scheme of VSG with inner loops to improve the stability is offered, and the appropriate value of virtual resistance is given. All the analysis above is verified by hardware-in-the-loop (HIL) experiments in Section 4. Finally, the conclusion is drawn in Section 5.

SEQUENCE IMPEDANCE MODELLING FOR VSG
In this section, the impedance models of VSG with and without the inner loops are built in detail and simulations are built to verify the accuracy of analytical models that are prepared for further stability analysis in the next section.
A typical VSG control scheme with inner loops is shown in Figure 1. The power-control loops contain active power and reactive power control, which aims at mimicking the characteristics of synchronous generators. The active power control is designed to imitate the characteristics of primary frequency regulation and the swing equation of rotor as shown in Equation (1): where ω s is the rated radian frequency, J is the virtual inertia, D is the damping coefficient, P m is the virtual mechanical power, P ref is the active power instruction and P e is the electric power, k p is the P-ω droop coefficient, and θ is the output phase of VSG.
The reactive power control is to imitate the voltage regulation as expressed in Equation (2): where E is the virtual inner electric potential and E ref is the instruction of inner electric potential; Q ref is the reactive power instruction and Q is the output reactive power; and k q is the Q-V droop coefficient.
The inner loops contain current-control loop and voltagecontrol loop and each loop adopts PI controller to track the reference signal. As for the main circuit, assuming that the high-frequency current flowing through the inductor in steady-state can be neglected in the process of modelling, then the expression of the main circuit in frequency domain is as below: where V abc , I abc are the output voltage and current in a steadystate operating point; V abcpwm is the PWM signal; L f is the filtre inductance and R is the parasitic resistor; and s is the differential operator in frequency domain. The idea of sequence impedance modelling is to calculate the first-order current response to a harmonic voltage perturbation and take the ratio of perturbation voltage and current response as the impedance at corresponding frequency. Next, we will build sequence impedance model for VSG with inner loops in detail.
Since VSG control scheme in this study does not include the DC voltage control, DC-link voltage is assumed to be maintained constantly by former converters or batteries and thus regarded as an ideal DC voltage source [21,22,29]. To begin with, assume that the fundamental component of the output voltage and current of VSG are both threephase symmetrical and in positive sequence. After adding three-phase symmetrical small-signal perturbations to the output voltage of VSG, the output voltage and current of VSG can be expressed as follows (taking phase A as e.g.): where V 1 is the amplitude of output voltage, I 1 and φ i1 are the amplitude and phase angle of fundamental current, V p and V n are the amplitudes of the positive-sequence and negative-sequence perturbation voltages, I p and I n are the amplitudes of the positive-sequence and negative-sequence current responses, φ vp and φ vn are the initial phase angles of the positive-sequence and negative-sequence perturbation voltages, and φ ip and φ in are the initial phase angles of the positive-sequence and negative-sequence current response, respectively.

By transferring Equation (4) into the frequency domain we have
Then, using the Clark-Park transformation, we can obtain the expression of them in the DQ-rotating frame: According to the convolution theorem, multiplication in time domain equals convolution in frequency domain, active and reactive power follow as shown in Equation (8): As for the power loops, the output signal of reactive power loop can be treated as a constant value [22]. Therefore, only the small-signal equations of active power loop are considered and can be expressed as below: Combining the above equations, the small signal of output phase in frequency domain is expressed as below: where M p (s) = (J s s + D + 1∕k p )s represents the transfer function of VSG-control loop. The original Clark-Park transformation matrix T dq in time domain is where θ 0 is the original output phase in a steady-state point.
When the small signal of phase angle ∆ θ takes place due to the power loop control, it will cause small signals on each term of T dq . Taking the first column of T dq as an example, when ∆ θ takes place, cos(θ 0 + ∆ θ) and -sin(θ 0 + ∆ θ) will be expressed as Equation (12), and the rest of terms in T dq can be expressed similarly: From the calculation above, by extracting the coefficient of each term, we can obtain the expression of the new Clark-Park transformation matrix T′ dq after ∆ θ takes place in time domain as follows: By combining Equations (11) and (13), T′ dq in time domain is expressed as where T dq is defined as Equation (15): According to the convolution theorem, the Clark-Park transformation matrix in frequency domain takes the form as follows: where X [f] represents the expression in frequency domain of time domain signal X. Similarly, the inverse Clark-Park transformation matrix is where . With the new transformation matrixes above, the output voltage and current in DQ domain can be expressed as These signals are the feedback signal involved in the inner loops of VSG. As for the inner loops, the output of voltage loop, that is, the current reference is where is the voltage regulator. Similarly, the output of current loop, that is, the modulation signal in DQ domain is where K i (s) = k cp + k ci s is the current regulator. Finally, transferring Equation (20) into the three-phase domain by Equation (17), the modulation signal can be obtained as After acquiring the small signal of Equation (21) and substituting it into Equation (3), the output impedance can be obtained as We can reorganise Equation (22) into a block diagram and depict it in a diagram as shown in Figure 2. The inner loops are depicted in the red-dashed line boxed area, and VSG power loops can be seen in the green-dashed line boxed area. From this figure, if the inner loops are removed from the control scheme, then the red-dashed line boxed part should be removed in the impedance model, thus the output impedance of VSG without inner loops would be Equation (23), which is consistent with previous studies [22].
where H ′ (s ∓ j 2 f 1 ) = 3 4 jM p (s ∓ j 2 f 1 ), whose components are simpler than H (s ∓ j 2 f 1 ) in Equation (22) as the output of the power loop does not go through the inner loops before being sent to the modulation module.
To verify the analytical models above, simulation models are established using MATLAB/Simulink, and parameters used in simulation models are listed in Table 1.
For convenience, perturbations and the impedance measurement devices are set on the grid side, thus the measured impedance in simulation is the total impedance of VSG and line impedance in the main circuit and is expressed as As shown in Figure 3, the theoretical model considering inner loops (i.e. Z pt analytical) matches well with the frequencysweeping results in simulation (i.e. Z pt simulation). In addition, it is obvious that with the same parameters of VSG controller, impedance models considering and ignoring inner loops differ enormously, indicating that the model Z pt of VSG-overlooking inner loops cannot present the output impedance characteristics for VSG in actual applications.

IMPEDANCE CHARACTERISTICS AND STABILITY ANALYSIS
From the previous section, in Figure 3(a), the phase angle of positive-sequence impedance of VSG with inner loops is around -90 degrees in low-frequency region, showing capacitance characteristics. Since in the power system, the capacitance impedance is our main concern of oscillation, positive-sequence impedance will be the focus of theoretical analysis in the remainder of this study.

Stability analysis
According to previous research [27], VSG control-based inverters can be regarded as a voltage source, and the topology of the system can be simplified as Figure 4. In Figure 4, the current flowing through the transmission line can be expressed as In Equation (25), V VSG , and V grid are both stable and Z grid is passive impedance. Thus (V VSG -V grid )/Z grid is stable. Therefore, the stability of the system depends on 1/(1 + Z VSG /Z grid ). Based on the Nyquist criterion, an improved criterion is proposed in [30] that the system stability can be determined by reading the phase margin of Z VSG /Z grid at the intersection of impedance-amplitude curves of Z VSG and Z grid . At a point of intersection, if the phase margin is below 0 degrees, the system will be unstable; if the phase margin is positive but very small, the system will have the possibility of oscillation near this frequency when perturbation occurs but will eventually stabilise. The closer the phase margin is to 0 degrees, the higher the possibility of oscillation in the system [25,30].
In this study, the filtre capacitor is treated as a part of impedance of grid, Z g , which is expressed in Equation (26):  Figure 5(a), the impedance-amplitude curve of VSG with inner loops and that of the grid intersect at 37.6, 47, 54, 87, 710 and 1100 Hz with the phase margins of -0.05, 10, 180.7, 180, 168.83, 42.74 degrees, respectively. Among these intersections, at 37.6 Hz, the phase margin is -0.05 degrees, which indicates instability and thus is named here as 'unstable intersection'. As for Figure 5(b), the impedance curve of VSG-ignoring inner loops and that of the grid intersect at 77 and 1750 Hz, where the phase margins are 112.38 and 18.29 degress, respectively. The phase margins are too large to cause oscillation, suggesting that the system will be predicted to be stable if the inner loops are not taken into consideration. Figure 5 reveals a significant difference in the stability analysis by the impedance models considering and ignoring the inner loops of VSG, showing that the inner loops bring the risk of instability that cannot be predicted by the impedance model of VSG-overlooking inner loops. Therefore, they should

Parameter analysis
After knowing that inner loops make an enormous difference to the output impedance of VSG, the influence of each parameter on impedance is studied in this section.

Voltage-control loop
The influence of parameters of voltage-control loop is investigated and the results are depicted in Figure 6. As shown in Figure 6(a), the proportional coefficient k vp has a minor effect on impedance in a low-frequency region. In a high-frequency region, with the increase of k vp , the amplitude and phase of VSG decrease. Nevertheless, Figure 6(b) shows that the integral coefficient k vi has significant impact on the impedance amplitude in a wide range of frequency. When k vi increases, the impedance amplitude of VSG decreases, and the unstable intersection of the impedance curves shifts to lower frequency but is not eliminated and the phase margin of the intersection is still below 0 degrees. Therefore, if the impedance is required to change substantially in a low-frequency region, then modifying k vi will be an efficient approach. However, the intersections of the curves of impedance amplitude in a low-frequency range can only be changed but hardly eliminated. That means, the frequencies of oscillation may be changed by adjusting k vi but the oscillation itself can hardly be eliminated by adjusting k vi .

Current-control loop
The influences of the current loop parameters are shown in Figure 7. As shown in Figure 7(a), when the value FIGURE 9 Stability analysis of VSG with virtual impedance of k cp changes, both the amplitude and the phase angle of impedance will change in a high-frequency region while they almost stay unchanged in a low-frequency region. The impedance amplitude of VSG increases in a high-frequency region along with the increase of k cp . Figure 7(b) shows that the value of k ci makes hardly any difference to the impedance. From this perspective, to improve the dynamic performance of VSG without changing its output impedance, k ci is the appropriate one to be adjusted, whereas to change the high-frequency part of impedance, changing the value of k cp is an efficient way.
As shown in Figures 6 and 7, even though the inner loops impact the output impedance of VSG to a huge extent, the oscillation cannot be avoided only by adjusting the value of inner-loops parameters. Therefore, the corresponding solution for oscillation needs to be proposed.

Stability improvements
Plainly, the most direct way to improve the stability is to revise the impedance by adding virtual impedance module into VSG-control scheme. When designing the virtual impedance to avoid the instability in low frequency caused by the inner loops, the solution of adding a virtual resistor rather than a virtual inductor or virtual capacitor in control scheme is adopted in this study as shown in Figure 8, since virtual inductor is not effective in revising low-frequency impedance and virtual capacitor may cause oscillation in a high-frequency region.
The revision effect of different virtual resistance on the output impedance is shown in Figure 9. It shows that the amplitude and phase of output impedance increase in a lowfrequency region along with the increase of virtual resistance. With a 0.05 Ω virtual resistance added to the control scheme as shown in Figure 9, the phase margin at the intersection is enlarged to around 15 degrees, meaning the system is stable but the damping is not enough to prevent dynamic oscillation during dynamic process. With a 0.5 Ω virtual resistance, the amplitude of VSG impedance increases so that there are no intersections in a low-frequency region, indicating better dynamic performances without oscillation in low frequencies.
The larger the virtual resistance is, the more sufficient the damping to oscillation is; however, too large a virtual resistance is unbeneficial to the decouple control of active and reactive powers [31]. Therefore, a small virtual resistance that is enough to make the impedance amplitude curve of VSG rise to the position where it does not intersect with that of the grid is recommended here.

STABILITY VALIDATION BY EXPERIMENTS
In this section, HIL experiments [31][32][33] are conducted to verify the accuracy of stability analysis and the effectiveness of the proposed method of impedance correction.
The HIL system is shown in Figure 10. In the HIL system, the plant model (initially built with MATLAB/Simulink) is first compiled in the host machine and then downloaded into the target machine for real-time emulation (with a main step size of 8 μs). The control strategy runs separately in a digital signal processor (DSP) TMS320F28335 with a clock step of 1/150 μs. The voltage and current signals, generated according to the realtime model in the target machine, are suitably scaled to output via a multifunction I/O card Humusoft MF624 embedded in the target machine. These analog signals are sent to the DSP peripheral circuit for further processing. The modulation wave generated by the DSP is transferred to the target machine by an inverse process. Finally, an oscilloscope is used for real-time monitoring and logging of the voltage and current waveforms provided by the target machine and frequency and power waveforms provided by the DSP.
The tested topology of experiments is the same as that in Figure 1 with parameters in Table 1.
When the inverter controlled by VSG with inner loops connects to the grid with a line inductance of 1 mH, the waveforms of output current of phase A i a , active power P e and frequency f are shown in Figure 11. It shows that the system is unstable and oscillating. The FFT analysis of i a in Figure 11(e) shows that the maximum components of the oscillation are around 38 Hz.
As demonstrated in Figure 5(a) in Section 3, the theoretical analysis result based on the impedance model considering   inner loops of VSG indicates that the system is unstable and will oscillate around 37.6 Hz, which is consistent with the experiment result. Nevertheless, the theoretical analysis result based on the impedance model ignoring the inner loops of VSG in Figure 5(b) indicates that the system is stable, which does not agree with the experiment result.
Obviously, the experiment result verifies that the theoretical stability analysis based on the impedance model with the inner loops of VSG is accurate to reveal the risk of instability of the practical system correctly, while the impedance model overlooking the inner loops of VSG cannot predict the risk of instability that is very dangerous to the system. Therefore, the inner loops of VSG cannot be overlooked in the impedance model. Figure 12 shows the virtual resistor after 0.05 Ω is adopted in the control scheme under the same set of parameters, i a , P e and f. It shows that the system is stable. However, when a disturbance of the grid phase of 5 degrees takes place at t 0 , the system responds to the disturbance with dynamic oscillation. Due to the oscillation, the current increases rapidly to approximately 80 A and the fluctuation of active power and the frequency is around 2000 W and 1.6 Hz, respectively. The phenomenon that the system returns to the steady-state after dynamic oscillation indicates that the damping of the system is enough for stability but still not sufficient to prevent dynamic oscillation, which is consistent with the theoretical analysis Section 3. Nevertheless, a virtual resistor after 0.5 Ω is adopted in the control scheme under the same set of parameters, i a , P e and f, is shown in Figure 13. In this case, the system is also stable. Moreover, it has a better dynamic performance without oscillation when a disturbance of the grid phase of 5 degrees takes place at t 0 . This verifies that the recommended virtual resistance of 0.5 Ω to eliminate the intersections of impedance-amplitude curves between VSG and the grid in Section 3 indeed provides enough damping to achieve a good dynamic performance.

CONCLUSION
With an aim at the problem that the existing sequence impedance models ignoring the inner loops of VSG are not accurate enough for stability analysis in practical applications, this study provides an accurate sequence model and stability analysis considering the inner loops of VSG. To begin with, a sequence impedance model for VSG with inner loops is built and presented into an intuitive diagram, showing that the inner loops have a significant influence on the output impedance of VSG. Then, the stability analysis results show that the inner loops bring in the risk of instability and oscillation that cannot be indicated by the impedance models overlooking them. Moreover, the role of each parameter of the inner loops is further researched and the study points out that the values of proportional coefficients in the inner loops will influence the output impedance of VSG in high frequency. The value of integral coefficient of the voltage loop will influence the amplitude of impedance in a wide range of frequency. Even though they can affect the impedance to an enormous extent, the oscillation can hardly be eliminated by adjusting their values. Thus, a corresponding solution to ameliorate oscillation by introducing virtual resistor into VSG is adopted and its appropriate value is studied. Finally, the experiments are implemented, and the time domain results verify the accuracy of theoretical analysis and the effectiveness of the adopted virtual resistance.