Analysis and design of gradient descent based pre‐synchronization control for synchronverter

Funding information Department of Science and Technology, Ministry of Science and Technology Abstract Synchronverter (SV) control has emerged as a popular method for distributed energy resources (DERs), to emulate response of a synchronous generator. In this work, a simple gradient descent based pre-synchronization control for SV scheme is proposed that varies the reference frequency in SV control alone. Thus, local load connection to DER can remain intact during synchronization with proposed pre-synchronization method, unlike virtual current based methods. Normally, phase-locked loop used for synchronization purpose, uses a first order loop filter such as a PI controller. In the proposed presynchronization control, the inherent low pass filter of SV scheme itself is used as a loop filter. Transient response analysis is presented in this work, based on small signal transfer functions derived from the proposed method. From the theoretical analysis of proposed pre-synchronisation control, design of the parameters is presented. Thus, there is no trial and error basis for parameters tuning in the proposed method, as compared to virtual current based methods. Validation of proposed pre-synchronisation control through experiments are presented for all initial conditions. The transient response analysis, effectiveness of proposed method during local load changes and grid integration are verified by experimental results.


INTRODUCTION
The usage of distributed energy resources (DERs) has been steadily increasing for utility grid systems and microgrid systems as well. In the conventional current controlled DERs, there are drawbacks relating to the transient behaviour, which in turn raise stability concerns [1]. In order to solve these issues, several concepts like virtual inertia [2,3], virtual synchronous generator (VSG) [4,5], synchronverter (SV) [6], etc. have been proposed lately, in order to mimic behaviour of synchronous generators (SG). The SV control is a popular one among them and there have been several improvements [7][8][9][10][11] to the original SV control. An important improvement is the selfsynchronisation feature as given in [11]. With the usage of selfsynchronisation feature, the DER voltage is synchronised with the grid voltage during the start-up stage of DER and thereby eliminating the need of a phase-locked loop (PLL). The process This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited. © 2020 The Authors. IET Renewable Power Generation published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology of synchronising DER voltage to grid voltage, before connecting DER to the grid is known as pre-synchronisation. This process is necessary so as to avoid the high inrush current while connecting DER to the grid. The self-synchronisation feature in [11] was based on the concept of reducing a virtual current to zero. The virtual current is fed to the SV control instead of the actual inverter current and it is calculated from the inverter voltage, grid voltage and a virtual impedance. However, the virtual impedance is tuned by trial and error. The concept of virtual current based self-synchronisation, is developed from the simple circuit of SG connected to an infinite bus source. But in this circuit, when the phase difference between SG and bus voltage is beyond − ∕2 or + ∕2, the rotor of SG rapidly accelerates and loses synchronisation with the infinite bus. The response during selfsynchronisation process for the aforementioned scenario has not been discussed in [11]. Also, an additional PI controller was used during synchronisation to generate the incremental reference frequency, without detailing the design of PI controller parameters.
In [12], the resemblance between structure of droop control and PLL was used along with virtual current concept of [11], to demonstrate self-synchronisation ability for droop controlled DERs. The self-synchronisation concept in [11] was also applied to the universal droop control scheme in [13]. A currentlimiting droop control for a single-phase system was proposed in [14], along with the self-synchronisation ability based on virtual current concept in [11]. However, the synchronisation performance with initial phase difference beyond − ∕2 or + ∕2 has not been addressed in [12][13][14]. In [15], a single-phase SV with current limitation capability has been proposed and the virtual current concept of [11] was used for self-synchronisation. A term based on ∕2 phase shifted voltage was added to the reference voltage generation and due to this term selfsynchronisation was achieved for the full range of initial phase difference, that is, (− , + ). In [16], a self-synchronising threephase SV control is presented, where a virtual resistance branch is used for calculating virtual active and reactive power feedback signals. A coordinate transformation was used while calculating virtual active and reactive power signals, which allows synchronisation for the full range of phase difference. Even though the problem of higher initial phase difference was addressed in [15] and [16], there are other common drawbacks in virtual current based self-synchronisation methods. These drawbacks have been highlighted in the following subsection. PLL based presynchronisation methods was applied to VSG in [17][18][19] and their drawbacks have also been highlighted in the next subsection.

Motivation
When virtual current based self-synchronisation methods as given in [11][12][13][14][15][16] are applied, the actual inverter current cannot be fed to the SV control. Thus, virtual current based methods restrict the connection of local loads to DER, during synchronisation at start-up or at reconnection after fault clearance. Another common drawback of virtual current based presynchronisation methods is that the virtual impedance (virtual resistance in case of [16]) and other self-synchronisation parameters (additional PI controller, damping correction factor) are tuned by trial and error. Since the value of virtual impedance and other self-synchronisation parameters vary with power rating of DERs, there may be difficulty in tuning these parameters. Further, there may be difficulty in tuning the self-synchronisation parameters while considering all initial conditions. In PLL based pre-synchronisation methods for VSG [17][18][19], it is seen that there is no clear design method for the integral or PI control based frequency and phase regulators. Also, all initial conditions have not been considered while designing pre-synchronisation methods in [17][18][19], which may lead to slow synchronisation or even synchronisation failure.

Contributions
• Taking into account the above mentioned limitations, a simple gradient descent based pre-synchronisation method for SV control is proposed in this work. The structure of proposed pre-synchronisation control is such that, it only varies the reference frequency in the SV control. Thus, the inverter current feeding the local load can be given as an input to the SV control during synchronisation and local loads can remain connected to the inverter at all stages of operation. In order to make sure that local load operation is not affected during synchronisation, the SV frequency is limited to a certain range using a saturation block. Also, comprehensive analysis of SV frequency response and time taken for synchronisation is presented in this work for all initial conditions, which includes effect of SV frequency limits. • PLLs used for synchronisation purpose, has a loop filter along with a phase detector. The loop filter mainly removes the high frequency components after phase detection along with shaping dynamic response, and a first order loop filter such as a PI controller is generally used [20]. The gradient descent based minimisation method also requires a loop filter while applying it for synchronisation. Thus in the proposed pre-synchronisation method, the inherent low pass filter (LPF) of SV control itself is used as a loop filter, instead of an additional PI controller. • The transient response during pre-synchronisation varies with the variation in loop filter parameters. Hence, a tunable variable is added to the SV control, in order to vary the time constant of inherent LPF in SV control. Using appropriate small signal transfer functions, the analysis of transient response during pre-synchronisation is presented. Based on complete theoretical analysis for all initial conditions, design of pre-synchronisation control parameters using relevant equations is also presented in this work.
The paper is organised as follows. In Section 2, the detailed explanation for the usage of gradient descent method for synchronisation is presented. The complete implementation and analysis of proposed pre-synchronisation control for SV scheme is given in Section 3, along with a comparison study of proposed method with other self-synchronisation methods through simulations. The experimental validation of the proposed presynchronisation control is presented in Section 4 and the concluding remarks are given in Section 5.

APPLICATION OF GRADIENT DESCENT METHOD FOR PRE-SYNCHRONISATION
In order to connect a three-phase SG to the grid or point of common coupling (PCC), a pre-synchronisation control is initially used to match the amplitude, frequency, phase angle and phase sequence of SG and the grid voltages. In case of a SV controlled DER too, a pre-synchronisation control is needed Figure 1 Basic illustration of grid connected DER with local load before connecting to the grid or PCC through a breaker CB2 as shown in Figure 1. The amplitude matching can be easily taken care by varying the modulation index in the PWM unit of control according to the measured RMS value of grid voltage. The simple method for amplitude matching, along with appropriate expressions is presented in the next section. Thus, the phase and frequency matching of inverter voltage with grid voltage becomes an important problem of synchronisation, and the gradient descent method approach for this problem is discussed in detail below. Consider a balanced, 1 p.u. (peak) instantaneous three-phase grid voltage u abc of frequency g and a 1 p.u. (peak) instantaneous three-phase inverter output voltage y abc of frequency inv as given below.
The instantaneous phases g and inv used in above equations are defined as given below, with respect to t= 0 as reference.
Here, inv is the initial phase angle by which the inverter voltage leads the grid voltage at start of minimisation and this angle inv will remain as a constant during minimisation. Let an error signal be defined as given below.
This error signal should be reduced to zero or close to zero in order to achieve synchronisation. The shape of error signal before start of synchronisation will be that of a beat interference pattern, due to the error being the difference of two sinusoids with their frequencies being close to each other. Since the error can be positive as well as negative, a cost function proportional to the square of error is considered, which is defined below. .
Upon further simplification of (5) by substituting error signal, the final expression of cost function is obtained as given below.
From the expression of cost function, it is observed to be a convex function by considering ( inv − g ) as the variable for the full range of phase difference (− , + ). The minimum of zero value exists for the cost function when the variable ( inv − g ) is zero, that is, when synchronisation between signals y abc and u abc is achieved. As the cost function is convex and a minimum exists, gradient descent approach can be used to minimise this cost function. For this minimisation problem the frequency inv is varied alone, as the SV control directly controls the frequency of inverter voltage and not the phase angle of inverter voltage. Thus, the variable inv in this cost function is updated for every (i + 1) step by using the following equation until the convergence is achieved.
Here K l is known as the learning rate or hyper-parameter. The expression for differential of cost function C with respect to variable inv , which represents the slope of cost function is obtained in terms of the error signal as given below.
The above equation is obtained by omitting the time term t , in order to arrive at a time invariant equation. Since the time variable is always positive, the sign of slope does not get affected by this omission. The slope of cost function with respect to inv is further simplified by substituting the expressions for error signal and it is given below in different forms.
The expression in (8) is used in the implementation of proposed pre-synchronisation control, while the simplified form of (8) given in (9), is used for analysis. Upon substituting (9) in (7), the equation of updated frequency during minimisation is obtained as given below.
The following subsection begins with the analysis of gradient descent minimisation for the case of no limits on frequency inv . This analysis helps in understanding, how the instantaneous phase difference and frequency difference are reduced by varying inv alone. Since there is a local load connected to the inverter during synchronisation, inverter frequency should remain within a specified range, so that local load operation is not affected. Thus, the gradient descent minimisation for frequency being limited within the range of 49.5 and 50.5 Hz is analysed. Numerical simulations for both cases are also presented in the next subsection. It should be noted that, the loop filter in a PLL adds the transient behaviour to the output of phase detector and gradient descent method is a phase detector in this case. Thus, the analysis without a loop filter as given in next subsection, helps in understanding how minimisation at steady state can be achieved, with and without frequency limits for different initial conditions.

Analysis of gradient descent minimisation method
The gradient descent minimisation or synchronisation process involves the reduction of frequency difference ( g − inv ) and reduction of instantaneous phase difference. As only the frequency inv is varied during minimisation, the frequency difference cannot be reduced in the beginning, when there is an initial phase difference, that is, when inv is non-zero. Thus, the phase difference caused due to inv will be reduced first, followed by reduction of frequency difference. The instantaneous phase difference ( g − inv ) = (( g − inv )t − inv ), will be first reduced to zero by either increasing or decreasing the frequency inv to a maximum or minimum peak. Later, the frequency inv will move towards the value of grid frequency g .
The value of frequency inv before start of minimisation will be that of nominal frequency. At the start of minimisation, if inverter voltage lags the grid voltage, that is, when inv lies in the range of (-,0), the term ( g − inv ) is positive and hence incremental frequency will be positive at the start. Whereas, if inverter voltage leads the grid voltage at start of minimisation, that is, when inv lies in the range of (0, ), the term ( g − inv ) is negative and hence incremental frequency will be negative at the start. From (10), it is seen that the incremental frequency is directly proportional to sin( g − inv ). Thus, if inv is in the range of (-,0) there will be a maximum peak during minimisation and if inv is in the range of (0, ) there will be a minimum peak during minimisation.
Consider the minimisation is started at t=0, and time t=t p , be the instant when frequency inv reaches the peak (p) inv . Due to instantaneous phase difference ( g − inv ) being zero at t=t p , the following expression is obtained.
The above expression is valid for all inv in the full range of (− , + ). From (11), it is inferred that for a given K l , the time t p will be constant and the peak frequency (p) inv will increase, with increase in inv . Besides, it should be noted that even though the term ( g − inv ) becomes zero at instant t p , the steady state minimum has not been attained yet, as inv is not equal to grid frequency. Thus after t p , the frequency inv will move towards the grid frequency from peak value of (p) inv . When there are limitations on frequency inv , it may not reach the peak frequency in order to reduce the initial phase difference. Thus, the frequency will either be at the upper or lower limit (l ) inv for a particular time t lim , in order to reduce the instantaneous phase difference ( g − inv ) to zero. When Numerical simulation response of (a) frequency f inv , (b) cost function C and (c) error signal e a for gradient descent minimisation, with and without frequency limits two sinusoids are at slightly different frequencies for a particular time, the difference between two sinusoids will be that of a beat interference pattern. Hence, based on the theory of beat interference, relation between the frequencies (l ) inv and g , time t lim and the initial phase difference inv is obtained as given below.
The frequency (l ) inv corresponds to either 50.5 or 49.5 Hz for negative initial phase difference or positive initial phase difference, respectively. The steady state minimum has not been attained yet at instant t lim , as the frequency inv is not equal to grid frequency. From (12), an important conclusion can be made that the time t lim increases linearly with increase in magnitude of inv .
In order to verify the above analysis and expressions, numerical simulation results of gradient descent based minimisation for the cases of frequency without any limits and with limits are presented in Figure 2. The response given in Figure 2a is that of inverter frequency f inv in units of Hz. For this simulation, the frequency of grid voltage is fixed at 50 Hz, while the initial phase difference inv is set to -/2 (-1.5708 rad). The initial frequency of inverter voltage is set at 50 Hz and the learning rate parameter is taken as 0.01 for all numerical simulations inv from simulations are used to calculate the phase angle inv using expressions (11) and (12). The calculated inv are -1.57 and -1.572 rad for cases of frequency without limits and frequency with limits, respectively. With the calculated inv being close to the actual phase angle of -1.5708 rad, expressions (11) and (12) are verified for this particular initial condition.
From Figure. 2b,c it can be seen that for the case of frequency without limits, the cost function C and phase-a error e a reduce close to zero around t=0.25,s. However, for the case of frequency with limits, the cost function and error steadily decrease to a small value around t=0.5,s. From the numerical simulation for frequency without limits, it is evident that the deviation of inverter frequency from nominal value will be high for a large initial phase difference. Thus, saturation limits on inverter frequency is necessary, when local loads are connected during synchronisation.
The proposed method achieves synchronisation by two stages: initially the SV frequency stays at either upper limit or lower limit for a time t lim which depends on the initial phase difference and grid frequency; after t lim , the SV frequency reaches the grid frequency value. From (12), an important inference can be made that the time t lim decreases with increase in the range of frequency limits. For example, if the limits were 47.5 and 52.5 Hz, then the time t lim will be 1/5th when compared to case of 49.5 and 50.5 Hz limits. Thus, the overall time taken for synchronisation decreases with increase of inverter frequency saturation limits.  In order to cover different initial conditions for frequency being limited, numerical simulations are presented for: (i) grid frequency of 50 Hz with different initial phase differences in Figure 3a; (ii) initial phase difference of + /2 (+1.5708 rad) with different grid frequencies in Figure 3b. The time t lim for different cases are obtained from the simulations in Figure 3 and using expression (12), the equivalent phase difference for all cases are computed. The actual phase differences and calculated phase differences for different cases in Figure 3a are shown in Table 1 and they are very close to each other. For the different cases in Figure 3b, the equivalent phase differences are calculated to be +1.573, +1.572, +1.57, +1.572, and +1.571 rad and these are also close to the actual value of +1.5708 rad. Therefore, expression (12) is said to be applicable for all range of initial phase difference and frequency difference conditions.

PROPOSED GRADIENT DESCENT BASED PRE-SYNCHRONISATION CONTROL FOR SV SCHEME
A standard PLL used for synchronisation, has a phase detector, loop filter and an oscillator as illustrated in Figure 4a. The loop filter has two functions: (a) control of frequency dynamic response so as to maintain stable synchronisation under different disturbances; (b) limiting the high frequency components from phase detector and sending the filtered output to the oscillator. A loop filter of first order is sufficient for a simple PLL in power systems applications and generally a PI controller is used as a loop filter [20].
In the proposed pre-synchronisation control, the inherent LPF of SV scheme is used as the loop filter as shown in Figure 4b. In the SV control, a LPF action is created by the active power-frequency loop, with SV reference frequency * syn as input and actual SV frequency syn as output. While implementing gradient descent minimisation in continuous state for any cost function, the slope of cost function with respect to the variable is multiplied with negative of learning rate and subsequently added to the initial value of the variable. Then, this sum is integrated to obtain the variable of the cost function. Hence in the proposed method, the incremental frequency term of (7) is added to nominal frequency n and the sum is sent through LPF of SV to obtain the SV frequency. It should be noted that LPF acts as an integrator for low frequency components. Since the sum of incremental frequency and nominal frequency is given as reference frequency to SV control, the incremental frequency term is represented as Δ * in Figure 4b.
The calculated frequency from SV control, that is, syn is fed to the saturation block, where the limits on SV frequency are defined. Finally, the phase syn is calculated from the output of saturation block. Thus, the similarity of proposed presynchronisation control with that of a standard PLL can be seen from Figure 4. The basic SV scheme is briefly presented in the next subsection, followed by the implementation and transient response analysis of proposed pre-synchronisation control.

Basic synchronverter scheme
Based on the mathematical model equations of a simple round rotor SG, the original SV scheme is derived in [5]. The expressions for electrical torque T e , instantaneous emf e syn and reactive power Q G shown in Figure 5, are obtained from SG model equations. The notationssin syn andcos syn used in equations of SV scheme are defined as given below for any general angle .s An active power loop is used in SV which serves the purpose of frequency droop control along with the regulation of active power. Based on the mechanical equation or the standard swing equation of a basic SG, the active power loop was derived and the equation governing this loop is given below.
The variable J in (14) is the total moment of inertia referred to rotor. SV frequency syn being the important variable of SV control, is obtained by the active power loop and upon integrating it, the phase output of SV control syn is obtained. The mechanical torque T m is calculated by dividing reference value  (14) and expression of electrical torque T e , the active power loop is implemented as shown in Figure 5. The reactive power control in SV is implemented using an integral control, with inputs of either difference between reference and actual reactive power, or difference between nominal RMS voltage and measured RMS grid voltage. Based on the principle of excitation control in SG, the output of reactive power control is set as excitation flux M f i f and thereby the amplitude of output voltage is controlled. The reactive power loop of SV control can be operated either in voltage droop control mode (S 1 is open, S 2 is closed) or fixed reactive power generation mode (S 1 is closed, S 2 is open). Generally, fixed reactive power generation with 0 VAr as reference is the preferred mode of reactive power loop operation for grid connected DERs and throughout the paper, this mode is used for simulations and experiments. Thus, in a SV control the input signals are the instantaneous inverter current i out , the RMS value of grid or PCC voltage V g , nominal voltage V n , active power reference value P * g and reactive power reference value Q * g . The output signals from the SV are the reference voltage e syn and phase syn , which are sent to the space vector pulse width modulation (SVPWM) unit, thereby generating the pulses for the inverter. Grid connection with fixed reactive power S 1 =1, S 2 =0, S s1 =0, S s2 =0, S v in position 1 Figure 6 Scheme of amplitude matching

Implementation of proposed pre-synchronisation control
The simple method used for amplitude matching of inverter voltage with that of grid voltage is illustrated in Figure 6. The switch S v shown in Figure 6 will be in position 2 during presynchronisation, so as to calculate amplitude of grid voltage. Thus, the modulation index will be varied according to grid voltage amplitude, which leads to matching of inverter and grid voltage amplitudes. After connection of DER to grid, the switch S v will be set to position 1. The amplitude calculation for a balanced three-phase voltage (v a , v b , v c ) is done using the expression below, where V m is the phase voltage amplitude [6].
In Section 2, the error signal is obtained from difference of p.u. voltage signals. This error signal is implemented using the threephase instantaneous SV voltage e syn , instantaneous grid voltage v g and RMS value of grid voltage V g as given below.
The slope of cost function as in (8), can be implemented using the error signal defined above andcos`s yn term of SV control. Hence, slope of cost function along with the learning rate K l , is used to calculate the incremental reference frequency Δ * as represented in Figure 5. In order to control the start and end of pre-synchronisation process, a switch S s1 is used before adding incremental reference frequency Δ * to the nominal frequency.
The sum of n + Δ * becomes the reference frequency * syn for SV control. Also, the droop coefficient is varied using a variable k ′ and a switch S s2 , so as to vary time constant of LPF in SV control during synchronisation. Since a single SV controlled inverter with a local load is considered in this work, change of droop coefficient during synchronisation does not affect the power supplied to local load. The saturation block with limits of 50.5 and 49.5 Hz is added for SV frequency before feeding it to the integrator as shown in Figure 5.
There are five switches in the control, that is, S 1 , S 2 , S s1 , S s2 and S v . The overall control has three possible modes of operation: pre-synchronisation mode, grid connection with voltage droop control and grid connection with fixed reactive power generation mode. The control always starts in the presynchronisation mode and upon completion of synchronisation, the control can be operated in either grid connection with voltage droop control or fixed reactive power generation mode. Also, it should be noted that the circuit breaker CB2 between inverter and the utility grid will be opened during presynchronisation mode and subsequently closed at the start of grid connection. The state of all switches in the control during the three modes are listed below.
• Pre-synchronisation mode: The switches S s1 , S s2 are closed and the switch S v is set to position 2. The state of switches S 1 and S 2 is not relevant during pre-synchronisation, as the reactive power loop is not involved in this mode. • Grid connection with voltage droop control mode: The switches S s1 , S s2 are opened and the switch S v is set to position 1. The switch S 1 is opened and switch S 2 is closed. • Grid connection with fixed reactive power generation mode: The switches S s1 , S s2 are opened and the switch S v is set to position 1. The switch S 1 is closed and switch S 2 is opened.
The various states of switches in the control for each mode have been summarised in Table 2.

Transient response analysis of proposed pre-synchronisation control
The transient response during pre-synchronisation is analysed by deriving the small signal based transfer functions in this subsection. The small signal analysis may not replicate the complete non-linearity of the system, as it linearises the system around an operating point. However, the small signal analysis method is robust enough to study transient responses and design control parameters as shown in [4], [8], [10] and [15]. Hence, small signal analysis is applied for the proposed pre-synchronisation method as well. When pre-synchronisation process is started, the equation of active power loop under this condition is as given below.
In (17), the different variables involved during synchronisation are observed to be T m , T e , Δ * and syn . Here, the effect of small change in incremental reference frequency on the change in SV frequency alone is considered. Hence, the variables Δ * and syn are replaced with the sum of operating point (Δ * o , syn o ) and small variation variable (Δ * ,ˆs yn ) as given below.
From the above expression, it is clear that the SV frequency during synchronisation is obtained using the inherent LPF of SV with a time constant ′ f = J ∕(D p (1 + k ′ )) and unity gain. In order to include the effect of gradient descent method into small signal analysis, the change in incremental reference frequency and change in SV frequency can be expressed as given below.Δ * = K l (ˆg −ˆs yn ) andˆs yn = sˆs yn .
Based on the final expression of incremental frequency from (10) and using approximations for small signals, first half of (20) is obtained. The change in SV phaseˆs yn is multiplied with s to obtainˆs yn , since SV phase is obtained by integrating SV frequency. The transfer function between small change in output phase and small change in input phase is analysed, so as to obtain the desired transient response by tuning the loop filter parameters. Hence, by substituting both expressions of (20) into (19), the transfer function between small change in phase of SV syn and small change in phase of gridˆg is obtained as given below.
Thus, the parameter in gradient descent method, that is, K l and the tunable time constant of LPF in SV, That is, ′ f , can be varied to obtain desired transient response. From (21), it is observed that the time taken by SV frequency to reach grid frequency after reduction of phase difference, depends on the time constant of LPF. By comparing (21) with a standard second order transfer function, the damping factor ( ) is obtained as given below.
The poles or the roots of the transfer function in (21) are calculated to be as given below.
The stability and dynamic performance can be analysed by calculating the poles denoted in (23) for different values of the two parameters, that is, K l and ′ f . Thus, the calculated poles are plotted for two cases: (i) fixed ′ f with increasing K l as shown in Figure 7a; (ii) fixed K l with decreasing ′ f as shown in Figure 7b. For first case, ′ f =10 ms and K l is increased from 1 to 100, while for second case K l =100 and ′ f is decreased from 100 to 2 ms. Hence, it is observed that with higher K l and lower ′ f , the poles move to the left side. By choosing desirable transient response and pole locations, the two parameters K l and ′ f can be determined. However, the influence of different initial conditions at start of synchronisation must also be considered while determining these parameters. Hence the process in selecting K l and ′ f has been detailed in the next subsection.

Design of proposed pre-synchronisation control
The incremental reference frequency Δ * is directly influenced by the learning rate K l . It should also be noted that, the value of Δ * upon completion of synchronisation must be equal to difference between grid and nominal frequency. Hence, while designing the proposed pre-synchronisation control, K l is first calculated and the tunable time constant of LPF in SV ′ f , is calculated later using the transfer function analysis. Based on the simplified expression of incremental frequency as given in (9), the parameter K l is calculated using the equation given below. Here, Δ * max is the maximum deviation of grid frequency from the nominal value under normal conditions. In this work, the value of Δ * max is taken to be (2 * * 0.5) rad/s. Based on the local grid conditions, the value of Δ * max can be chosen. The term conv corresponds to the instantaneous phase difference between grid and SV voltage after attainment of convergence by gradient descent minimisation. Thus, it is preferred to take a very small value for conv such as 1 o , while calculating K l .
In a second order transfer function, the damping factor is generally tuned to 0.707 for a fast and oscillation free response. After calculation of K l , the time constant ′ f can be calculated using (22) for a damping factor of 0.707 and thereby calculate the value of k ′ .

Comparison study
In this subsection, a comparative study of the proposed pre-synchronisation control with virtual current based selfsynchronisation methods [11,16], is presented. From the structure of proposed method given in Figure 5, it is clear that the measured inverter current will not be removed from SV control during synchronisation. Thus, local load can remain connected to DER during synchronisation with the usage of proposed method, unlike virtual current based methods. Further detailed comparison based on synchronisation performance, time taken and parameters design process is given below along with appropriate MATLAB/Simulink simulations. The single phase equivalent configuration of grid connected DER as shown in Figure 8, is used for simulations. The parameters of configuration and the basic SV control used for all simulations are given in Table 3. The self-synchronisation parameters for methods in [11,16] were tuned by trial and error for the simulations. In the proposed pre-synchronisation control, the value of K l is first determined using (24), by considering Δ * max to be (2 * * 0.5) rad/s and conv to be 1 o . Upon calculation, K l is obtained as 180 rad/s. In order to obtain damping factor of 0.707, time constant ′ f is calculated using (22). Thus, ′ f is obtained as 2.8 ms and eventually the value of k ′ is calculated to be 2.571 for J ∕D p of 10 ms. Thus, the corresponding poles are −178.6± j 178.6 and with the poles being stable, the designed values of K l and k ′ are used.  Figure 9 (a, b) Simulation results of self-synchronised synchronverter in [11]. (c, d) Simulation results of proposed pre-synchronisation control with SV frequency limits of 49.5 and 50.5 Hz The error e abc as given in (16), is calculated for all simulations to determine completion of synchronisation. Along with error e abc , the SV frequency is also plotted for all simulations. For all the simulations given in this subsection, the grid frequency is set to 50.1 Hz, so that a frequency difference is created. The saturation limits of the SV frequency is taken as 49.5 and 50.5 Hz for first case of comparison. The simulation results of self-synchronised SV as given in [11] and the proposed pre-synchronisation control is as shown in Figure 9. The presynchronisation was enabled at t=1s and the phase difference at t =1s was +125 o for both cases. It is mentioned in Section 1 that self-synchronisation method in [11] may not be successful when initial phase difference is beyond the range of (− ∕2, + ∕2). Thus, this can be verified as the error e abc does not reduce to zero, due to the initial phase difference being +125 o . The SV Figure 10 (a, b) Simulation results of fast self-synchronising SV with coordinate transformation in [16]. (c,d) Simulation results of proposed presynchronisation control with SV frequency limits of 45 and 55 Hz frequency response shown in Figure 9b, reaches the grid frequency of 50.1 Hz in spite of unsuccessful synchronisation and this is due to the additional PI controller in the active power loop. The simulation results for the proposed presynchronisation control show that synchronisation has been achieved as the error e abc is reduced to zero. Also, the SV frequency reaches grid frequency of 50.1 Hz from the lower limit 49.5 Hz, with the desired transient response. Using the initial phase difference of +125 o in (12), the time t lim is calculated to be 0.578 s and it is close to the actual time of 0.576 s as observed from simulation.
In [16], virtual current based method is used to obtain fast synchronisation for the full range of phase difference. In the proposed pre-synchronisation control too, fast synchronisation can be achieved by having higher saturation limits on SV frequency and these are taken as 45 and 55 Hz for simulations. Thus, the synchronisation time is compared, for the method given in [16] with the proposed pre-synchronisation method through simulation results as shown in Figure 10. The presynchronisation is enabled at t =1s and the phase difference at t =1s is +105 o for both cases. The simulation results of Figure 10a,b for the method in [16], show that within 100 ms the error has been reduced to zero and the SV frequency has reached the grid frequency of 50.1 Hz. For the proposed method too, the simulation results in Figure 10c,d shows that fast synchronisation within 100 ms is achieved and the desired Figure 11 (a, b) Simulation results of a three-phase SRF-PLL transient SV frequency response is also obtained. The main advantage of proposed method over the method in [16], is simple calculation of control parameters and detailed discussion on this is given later in this subsection. The time t lim from Figure 10d is observed to be 53 ms and it is close to the calculated value of 57 ms using (12). Thus, the expression (12) is verified for different frequency limits. Further, the speed of synchronisation for the proposed pre-synchronisation method is compared with that of a standard three-phase synchronous reference frame (SRF) PLL as given in [20] through simulations. A standard SRF PLL was simulated with the same initial conditions as in the case of simulations presented in Figure 10, that is, intial phase difference of +105 o and grid frequency of 50.1 Hz. By comparing simulation of proposed method in Figure 10 with that of SRF PLL in Figure 11, it can be seen that the synchronisation speed of proposed method is similar to that of a SRF PLL. Thus, fast synchronisation performance as in case of a SRF-PLL, is also achievable by the proposed pre-synchronisation method. Even though synchronisation time for the method in [16] and the proposed method are almost the same, one of the main advantages of the proposed method lies in the simple calculation of pre-synchronisation control parameters. In the original self-synchronisation method [11], parameters including virtual impedance and a PI control had to be tuned by trial and error. For the method proposed in [16], parameters including virtual resistance, damping factor and a parameter in reactive power loop had to be tuned by trial and error. Due to virtual current based self-synchronisation, the parameters vary with power ratings of DER and this leads to difficulty in parameters tuning. Further difficulty in tuning of parameters may arise while ensuring successful synchronisation for all initial conditions, that is, maximum phase difference and maximum frequency difference. The parameters design of proposed pre-synchronisation control as given in previous subsection, is based on equations derived from the gradient descent method analysis and the transient response analysis. From the parameters design equations, it can be seen that the parameters are independent of power ratings. Also, all initial conditions have been considered in parameters design, which ensure successful synchronisation for all conditions. Hence, the design of pre-synchronisation parameters for the proposed method is much more simpler upon comparison with virtual current based self-synchronisation methods in [11,16].

Simulation for unbalanced and distorted grid voltage
The simulation results of proposed pre-synchronisation method for unbalanced and distorted grid voltage condition of 50.1 Hz, with SV frequency limits of 50.5 and 49.5 Hz is presented in Figure 12. The grid voltage as shown in Figure 12a, consists of 5% unbalance in phases a and c, along with fifth harmonic component of 10% and seventh harmonic component of 5%.
The pre-synchronisation is started at t =1s and the initial phase difference is +150 o . From Figure 12b, it can be seen that the SV frequency reaches the grid frequency and it has a ripple of approximately ±0.04 Hz due to the distorted grid voltage. The error e abc caused due to the initial phase difference and frequency difference, reduces from a high value of 2 p.u. to 0.1 p.u. as shown in Figure 12c. The error e abc settles to 0.1 p.u. after synchronisation, as the pre-synchronisation method is designed  Figure 12d,e shows that the phase difference between SV and the distorted grid voltage has reduced. Thus, the simulation results show that the proposed pre-synchronisation is quite robust for distorted grid voltage.

EXPERIMENTAL VERIFICATION
The configuration used for simulations as shown in Figure 8, is also used for experimental verification. In this work, the VSC/inverter is considered to be fed by a constant dc source DER and the transformer TF is used either for isolation or step up purpose. Upon completion of pre-synchronisation, the breaker CB2 between output of the inverter and the PCC bus will be closed. An equivalent three-phase experimental setup of the configuration is used in this work as shown in Figure 13. The setup is integrated to the grid using a three-phase auto transformer, which is represented as 3 AT in Figure 13. Resistances of 60 Ω are used as the local load in the experimental setup. The SV control and configuration parameters given in Table 3 was also used for the experimental setup. Also, the parameters of proposed pre-synchronisation control used in experiment is the same as the parameters used in simulations, that is, K l = 180 rad/s and k ′ = 2.571. The saturation limits of the SV frequency is taken as 49.5 and 50.5 Hz for experimental verification. The analysis of proposed pre-synchronisation control for frequency with limits as given in Section 2, is verified by corresponding experimental results of the following first subsection. The results are presented for high positive and negative initial phase difference, with grid frequency being close to 50 Hz. In order to obtain high frequency difference test condition, the nominal frequency was varied beyond 50 Hz and the corresponding results are also presented in the first subsection. As only the performance of pre-synchronisation control is tested, local load was not considered for results in the first subsection. So as to verify the transient frequency response analysis given in Section 3, results with different time constant ′ f , are presented in the second subsection. Also, the effectiveness of pre-synchronisation control for changes in local load during synchronisation is verified by the results presented in second subsection. In the last subsection, the results corresponding to grid integration after closing of breaker CB2 are presented.

Results for different initial conditions
The experimental results for a high initial phase difference of around 150 o and grid frequency close to 50 Hz are as shown in Figure 14.
The SV frequency f syn in Hz, phase-a error e a , SV and grid voltages during the synchronisation process are shown in Figure 14a. At the instant t 1 , the proposed pre-synchronisation control is enabled and the voltages of SV and grid around this instant are as shown in Figure 14b. The SV frequency is at 50.15 Hz before t 1 as no local load was connected. The SV and grid voltages around the instant t 2 are shown in Figure 14c and it is seen that mismatch between the two voltages reduces as synchronisation progresses. The SV and grid voltages around the instant t 3 , that is, after completion of synchronisation, are as shown in Figure 14d. The response of error e a and SV frequency f syn in Figure 14a is similar to the simulation results shown in Figure 9c,d, as the e a steadily decreases to zero and the SV frequency reaches grid frequency with the desired transient response. Using inv of 150 o in (12), the calculated t lim is 0.83 s and it is close to the actual value of 0.82 s as observed from the result. If local load was connected before start of presynchronisation, the only difference in the response will be that the SV frequency will be lesser than 50.15 Hz before t 1 .
The experimental results for a negative initial phase difference of around −162 o are as shown in Figure 15. The SV frequency, error e a , SV and grid voltages during the synchronisation process are shown in Figure 15a. At the instant t 1 , the pre-synchronisation control is enabled and the voltages around this instant are as shown in Figure 15b. The mismatch between SV and grid voltages reduces during synchronisation process as shown in Figure 15c. The SV and grid voltages around the instant t 3 , that is, after completion of synchronisation, are as shown in Figure 15d. Using inv of −162 o in (12), the calculated t lim is 0.9 s and it is close to the actual value of 0.91 s. Thus, the results in Figures 14 and 15 verify that SV frequency will reach the lower limit for positive initial phase difference and SV frequency will reach the upper limit for negative initial phase difference.
High frequency difference condition is tested in this work by changing nominal frequency n to 50.4 and 49.6 Hz, while maintaining P * g at zero. Experimental results with a positive and negative initial phase difference for a nominal frequency of 50.4 Hz are shown in Figure 16a,b, respectively. Experimental results with a negative and positive initial phase difference for a nominal frequency of 49.6 Hz are shown in Figure 16c,d, respectively. The incremental frequency in units of Hz is represented as Δf * in Figure 16. A saturation of ±1 Hz was used while recording Δf * , so as to obtain the same scale as that of f syn . For all cases in Figure 16, synchronisation was successful as e a reduces close to zero and f syn reaches the grid frequency of around 50 Hz. From  Figure 16, it can be observed that difference between value of f syn after synchronisation and nominal frequency (50.4 Hz for Figure 16a,b, 49.6 Hz for Figure 16c,d) is equal to Δf * value after synchronisation for all cases. Also, these results show that LPF in the SV control functions as a loop filter to remove the high frequency ripples from output of gradient descent method, that is, Δf * .

Results with different ′ f and changes in local load
The results for different time constants ′ f are presented in Figure 17. For all cases, the synchronisation process was started at the instant t 1 and the local load was connected to inverter The results for J ∕D p = 10 ms with k ′ being zero and with k ′ = 2.57 are shown in Figure 17a,b, respectively. Due to ′ f being higher in Figure 17a, SV frequency has an oscillatory response. In Figure 17c, the response for J ∕D p = 20 ms with k ′ being zero is shown. The oscillations of SV frequency in Figure 17c are higher when compared to Figure 17a, due to  This leads to more oscillations in SV frequency and higher settling time taken by SV frequency to reach grid frequency and this behaviour is verified for different cases in Figure 17. At the instant when local load is connected, that is t 2 , the output power of inverter P out starts increasing to 180 W and f syn deviates from the grid frequency for all cases. But, f syn is restored back to the grid frequency after t 2 and this shows that synchronisation was maintained even after change in local load. The time taken to reach grid frequency after t 2 , increases with increase in ′ f as shown in Figure 17.
Experimental results for change in local loads during the synchronisation process are also presented here. In the first sequence as shown in Figure 18a, the pre-synchronisation control was enabled at t 1 and the local load was connected during synchronisation at t 2 . From the results, it can be seen that the synchronisation process is unaffected after connection of local load when SV frequency was at the lower limit. In the second sequence as shown in Figure 18b, the local load was initially connected at t 1 , followed by the start of pre-synchronisation control at t 2 and the local load was removed at instant t 3 . In this case too, f syn is restored to the grid frequency and the synchronisation is still maintained despite the removal of local load at instant t 3 .

Results of grid integration
The results corresponding to grid integration after completion of synchronisation are presented in Figure 19. The results in Figure 19a,b correspond to the case of local load being Figure 19 Experimental results of grid integration for (a, b) local load being connected; (c, d) local load not being connected connected to the inverter before grid integration and the results in Figure 19c,d are that of the local load not being connected. After successful synchronisation, the breaker CB2 is closed and the switches (S s1 , S s2 ) in pre-synchronisation control are opened at instant t 1 . From Figure 19, it is observed that there are no transients in voltages and currents after grid integration. The variation of SV frequency after t 1 in Figure 19a,c is similar to the response when a DER with standard SV control is integrated to grid as given in [6]. The peak value of SV frequency after t 1 in Figure 19c is higher when compared that in Figure 19a. This is due to the change in power P out from 0 to 250 W in Figure 19c, being higher than the change of 180 to 250 W in Figure 19a.

CONCLUSION
In this work, a simple gradient descent based presynchronisation control for SV scheme is proposed, wherein the reference frequency in SV control alone is varied. Thus, the measured inverter current can be fed to the SV control during synchronisation and the local load connection to DER is not disturbed with the usage of proposed pre-synchronisation control. From the analysis and simulations of gradient descent minimisation, it is evident that SV frequency will have a large deviation from nominal value while reducing phase difference. Thus, saturation limits are needed for the SV frequency during synchronisation, so that local load operation is not affected. It is shown that higher saturation limits for SV frequency can be taken to achieve faster synchronisation, but the local load connected in the configuration should be considered before determining the limits.
In the proposed pre-synchronisation control, gradient descent minimisation method acts as a phase detector and the inherent LPF of SV control itself is used as a loop filter. Transient response analysis is presented, based on the small signal transfer functions for the proposed method. Based on the analytical discussion of the proposed method, the design of pre-synchronisation control parameters with relevant equations are presented. From a comparative study, it is seen that the structure and design of parameters in the proposed method is simple, whereas the parameters in virtual current based methods are tuned by trial and error. Efficacy and analysis of the proposed pre-synchronisation control for all initial conditions are validated by experimental studies. Further, the transient response analysis, effectiveness of pre-synchronisation control for changes in local load and the grid integration of a DER with local load are verified by experimental studies.