A distributed control for accurate active-power sharing in islanded microgrids subject to clock drifts

Funding information Ministry of Science, Innovation, and Universities of Spain, Grant/Award Number: RTI2018-100732-BC22 Abstract Inverters-based islanded microgrids are operated by local digital signal processors, driven by their own local clocks. These local clocks have drifts affecting the clock signals which are used to control the inverters in real time. In this scenario, a steady-state deviation is observed in active power sharing, degrading the microgrid performance. This paper presents a new control scheme that improves the microgrid performance by cancelling the active power sharing error due to clock drifts. The study includes a theoretical stability analysis and a design procedure of the control parameters based on the dynamic characteristics. Finally, selected experimental results are obtained in a laboratory microgrid with four inverters. In this setup, each inverter was equipped with its digital signal processor with drifting local clock.


INTRODUCTION
Microgrids (MG) are power systems that integrate a large number of distributed generation units (DG), loads and storage systems using fast acting power inverters [1]. The MG operate both connected to the main grid or in islanded mode, which is the case study of this paper. In islanded mode, the control system is responsible for regulating the frequency and amplitude of the microgrid voltage. In addition, it must guarantee an accurate sharing of active power [2][3][4][5]. To achieve these objectives, a hierarchical control architecture is widely used which is divided in three control layers [6][7][8][9]. The primary layer is responsible for controlling the active and reactive power and is usually implemented by the wellknown droop control method. The secondary layer purpose is to correct the steady-state deviation introduced by the droop method. The tertiary control is the highest control layer and it is usually responsible for controlling the energy dispatching.
Focusing on the secondary layer, the control architectures can be decentralised, centralised or distributed. In the decentralised approach, each VSI uses local measurements to correct the deviations introduced by the droop method [2]. In the centralised case, the secondary control is implemented in a central regulation and active power sharing [23][24][25][26][27][28][29]. In [23] and [24], it is shown the robustness under the effect of the clock drifts on the droop-based control. However, it is appreciated a deviation of the active power sharing in steady-state. For the secondary layer, a steady-state analysis of distributed secondary control schemes is shown in [25]. In addition, a centralised control solution that achieves zero steady-state error in active power sharing is proposed. However, the centralised approach reduces the system reliability and the fault tolerance. A control scheme without communications is considered and studied in [26]. However, the local operation of this secondary control does not reach the level of quality obtained with communication-based controls. In [27], a consensus-based control is analysed, showing that the steadystate error in active power sharing is very sensitive to the variation of the control parameters. This low robustness behaviour affects the system performance, causing an inaccurate distribution of the power delivered by each inverter. In [28], an extended study of the steady-state effect on frequency regulation and power sharing in inverter-based islanded microgrid is presented. This study analyses different secondary control policies under drifting clocks, including a closed-loop model for each policy. Moreover, it also considers a recent alternative approach for frequency regulation and power sharing named droop-free control [18]. It is worth mentioning that all the policies analysed in [28] suffer error in active power sharing. Finally, [29] presented a solution to correct the error in active power sharing under clock drifts. This is a solution without communication. However, it only has a good performance at high load, having an inaccurate active power sharing at low and middle load conditions, delimiting the range of use.
Furthermore, some studies have proposed solutions based on the global positioning system (GPS) to the frequency restoration [30][31][32]. In [30], a power-angle (P-θ) droop control was presented, with a GPS communication for frequency synchronisation. However, this method presents an inaccurate activepower sharing due to the mismatch of the line voltage drops. In [31], a V-I droop control with a piecewise linear droop was presented to reduce the active power sharing error at high load conditions. However, these control schemes may become unstable in a GPS interruption. In [32], an adaptative droop control to ensure stable operation during GPS signal interruptions was presented. However, this method presents inaccurate activepower sharing at low and middle load conditions. Finally, an IEEE 1588 precision time protocol (PTP) was implemented in [28] to perform clock synchronisation. However, the study demonstrated that the application of the clock synchronisation protocol does not mitigate the problem caused by clock drifts.
The main contribution of this paper is a new control scheme that corrects the error in active power sharing and improve the performance of the MG under the presence of clock drifts. At the starting point, this study considers a distributed averaging control in the secondary layer. This base control architecture is next modified with a new control term in order to reduce the steady-state active power sharing error produced by the clock drifts. The new control scheme is driven with a communication service that provides accurate active power sharing for all load conditions under the clock drifts. This control improves the state-of-the-art control approaches, especially those reported in [28] and [29], with higher accuracy in active power sharing even in the presence of clock drifts, as shown in the experimental results. Moreover, a theoretical study including the dynamic closed-loop model of the system is presented. Based on this model, a control design procedure considering a stability analysis of the system is presented. Finally, selected experimental results are shown to validate the theoretical predictions and the superiority of the proposed control against other control approaches. The setup is based on a laboratory MG equipped with four inverters with local DSP driven by drifting internal clocks.
The paper is organised as follows. Section 2 presents the problem formulation, including the control objectives. Section 3 proposes a control scheme that improves the impact of the clock drifts on the active power sharing, including a dynamic model of the MG. Section 4 presents a procedure to design the parameters of the proposed control. The experimental results on the laboratory MG are presented in Section 5 which validates the theoretical results presented in the previous sections. Section 6 concludes the study.

PROBLEM STATEMENT
This section presents the inverter-based islanded MG model, the control objectives and the problem formulation. Figure 1 illustrates a diagram of the three-phase inverter-based islanded MG considered in this study. It is composed of several inverters that are modelled as a voltage source with a series impedance. In each inverter, the local reference frequency * i is calculated with local measures and data received from the communication network, and using local time coordinates t i given by local internal clocks.

Model of an inverter-based islanded microgrid with droop control policy
The inverters considered in this study are equipped with their own DSP that have an autonomous clock with a local time (t i ) that differ from each other (t i ≠ t i+1 ) due to the clock drifts. These local times can be written as a function of a global time t and the clock drift rates as [22]: where d i is the clock drift rate of the i th DSP local clock. In an ideal case, d i = 1 meaning that all clocks are ideal (i.e. the local times coincide with the global time). In practice, this situation is unrealistic because very small deviations (several parts per million) around d i = 1 are observed, which means that the time signals generated by each processor progresses at a different rate. Consequently, control actions based on these time signals are not accurate enough and may degrade the control performance.
In fact, they can produce a noticeable impact on the MG system operation as it is shown in [23][24][25][26][27].
The droop control is a widely used control approach, that uses the frequency to control the active power flow and the voltage to control the reactive power flow. It can be expressed as [2,6] where * i and E * i are the computed references for the frequency and amplitude of the inverter output voltage, m i and n i are the frequency and voltage droop gains, respectively, ω o and E o are the frequency and voltage at no load condition, and P i and Q i are the averaged active and reactive power. These variables are calculated using a low-pass filter (LPF) with cutoff frequency p and q as follows: where p i and q i are the instantaneous active and reactive output power of the inverter.
The computed references of frequency and amplitude are used to generate the reference output voltage as follows:

Control objectives
The control objectives for the VSIs considered in this study are formulated in steady state as follows: (i) To guarantee the active power sharing between the inverters, proportional to the power rating of each VSI [26]: where P i,ss,ID is the ideal active power of the ith VSI in steady state, P L is the global load and n is the number of VSIs. The power rating is giving by the relation between the droop coefficient of each VSI (i.e. m i ). In the particular case that the inverters satisfy m i = m j , for j = 1,…, n, the first control objective in Equation (8) can be written as P i,ss,ID = P L ∕n.
(ii) To regulate the frequency of the MG: where ω ss is the steady-state frequency of the MG and ω o is the nominal frequency.

Problem formulation
Due to the clock drifts, the local reference frequency of each inverter differs from the MG global frequency, as shown in [25]. Hence, a deviation is generated in the local frequency in steady state. These local references can be written as a function of the global frequency and the clock drift rates as [25]: * i,ss = d i ss (11) Therefore, due to the clock drifts and the frequency deviations, the active power injected for each VSI in steady state P i,ss is different to the ideal active power expressed in Equation (8). These deviations in frequency and active power can be calculated as follows:

CONTROL PROPOSAL
The main contribution of this study is the proposal of a new control scheme that eliminates the steady-state error in active power in all load conditions under the presence of clock drifts. In this section, the static and dynamic characteristics of the proposed control are derived.

Hierarchical control with communication
The MG follows a hierarchical control scheme, using the droop method in the primary control layer expressed in Equations (2) where i is the local correction term that can be generated by different techniques. Using the distributed averaging control presented in [10], the output of the secondary layer can be written as: where a is the weighted average error of the received VSIs correction terms, is the gain of the weighted correction term and K c is the integral gain, respectively. This secondary control uses a sparse communication network for exchange the value of j (t j ) among the neighbourhoods VSIs. Besides, the coefficients a ij determine the availability of communication between VSI i and j, thus indicating the set of nodes n i that exchange control data. However, this control scheme presents a deviation in the active power sharing due to the clock drifts, as stated in [27]. Figure 2 shows the operation of two VSIs with the basic control considered in this study. The black line corresponds to the VSIs working with ideal clocks, that is, t i = t i+1 . The blue line denotes the effect of the clock drift on the VSI i while the green line shows the effect on the VSI i+1 . Note that * i and * i+1 are different due to the different clock drift rates in both DSPs. However, both converters operate in steady-state at the same frequency, thus supplying different active power.
The deviations between the local frequencies cause an inaccurate active power sharing, degrading the microgrid quality. As it is shown in [28] the active power error depends on the control parameters and the clock drift magnitude. These parameters include the droop coefficients. The active power errors due the clock drifts can be calculated as follows: One of these parameters is the droop coefficient, that depend of the maximum power of each unit. It is usually designed as m i = Δ i,MAX ∕P i,MAX . Hence, a higher capacity will have higher active power error, thus deteriorating the microgrid performance. Therefore, a new control term is required to compensate the deviation in the active power and improve the MG performance.

Power control loop
A new control loop is proposed and added in the droop control policy (Equation 14). The main objective is to reduce the error in power sharing due to clock drifts and achieve the control objectives presented in Section 2. Figure 3 shows the desired operation of the inverters with DSPs with clock drifts. The red line denotes the steady-state of the new proposed control scheme. It should be noted that both inverters operate in steady-state at the same frequency and active power. To reach this operation, it is necessary to regulate the active power to a weighted averaged power that takes into account the power rating of the inverter. Taking this in mind, a new control term i is included to compensate the deviations in active power observed in steady-state, the new term can be written as: where K i is the integral gain and P a,i is the weighted average value of the active power of only the neighbouring inverters n i . Besides, to achieve the control objective presented in Equation (8), this weighted average power is calculated in Equation (19) using the power rating of the VSIs denoted as M i , that is, including the relation between the droop coefficients m j of the neighbouring VSIs, as expressed in Equation (20). It is worth mentioning that the proposed control uses sparse communication between the VSIs to receive both the active power P j and the droop coefficient m j from the neighbouring units to compute Equations (18) to (20) in real time. The new control scheme can be written as: * Figure 4 shows a diagram of the proposed control scheme. The primary layer uses the droop control in Equations (2) and (3) and the secondary layer the averaging control in Equations (15) and (16). The power control loop in Equations (18) to (20) is added to mitigate the effect of the clock drifts. As shown in the figure, the control system uses a low bandwidth communication network to interchange data between the neighbourhood sources.

Active power equilibrium point
This section presents the steady-state active power for the proposed control. The steady-state active power is derived by applying the analysis procedure presented in [26]. First, consider that the first-time derivative of the frequencies and active powers of the inverter is zero when time tends to infinite: Besides, the steady-state active power delivered by all inverters meets the MG load demand, that is, Thus, from the above considerations and from Equations (1), (11), (15), (16), and (18) to (21), the following expressions can be deduced Note that, from Equations (24) and (26), the final expression of the steady-state active power does not depend on the clock drift rates and coincides with the ideal expression in Equation (8). Therefore, with the proposed control, an accurate active power sharing is achieved for all load conditions, even in the presence of clock drifts. This interesting feature will be experimentally validated in Section 5.

Small-signal model
This subsection presents a small-signal model of the proposed control. This model is essential for the design of the control parameters introduced in Section 4. The model is written in the frequency domain using the Laplace transform starting from the expressions in global time t.
In this model, the variables are written in matrix form to compact the expressions. The active powerP i (t ) is denoted bŷ P (t ) = [P 1 (t ) …P n (t ) ] T , the local reference frequencieŝ * i (t ) byΩ * (t ) = [̂ * 1 (t ) …̂ * n (t ) ] T , the set point frequencieŝo(t ) bŷo = [̂o ,1 …̂o ,n ] T , the local computed correction termŝ i (t ) byΔ = [ 1 (t ) … n (t ) ] T , the proposed control termŝ i (t ) bŷ(t) = [̂1(t ) …̂n(t ) ] T , I is the identity matrix, 0 n×n and 1 n×n ∈ R R×R are n × n square matrices of zeros and ones respectively, and the diagonal matrices M and D ∈ R R×R of droop gains m i and clock drift rates d i , respectively.
The communication network can be represented by a connected unidirectional graph G c = {N c , E c } where the n c nodes N c represent VSIs that implement Equations (16), (19) and (20), and edges E c ⊆ N c × N c represent communication links. Parameters a ij form the adjacency matrix of G c such that a ij = a ji = 1 if nodes i and j can exchange their information and a ij = 0 otherwise [33].
By making explicit that the nominal frequency o is local to each inverter time (Equation 1) and that the local reference frequencies are function of the global frequency (Equation 11), the droop control algorithm given in Equation (21) can be written in matrix form as a function of the global time and the clock drifts as:̂ * Applying the Laplace transform to Equation (27), s being the Laplace operator and applying the change of scale property of Laplace transform that allows expressing a function of drifted time as a scaled function of the scaled complex variable s, the control algorithm can be rewritten aŝ where the clock drifts dependency has been made explicit.Δ(s) andΦ(s) can be expresed as follows: In Equations (29) and (30), L Δ and L P are the Laplacians of the secondary control loops and the proposed control loop, respectively. Besides, T d (s) is the communication delay presented in the neighbourhoods' data used by the frequency and active power control loops. It has been modelled as: (34) where T r is the transmission rate. From Equation (29), the output of secondary control layer can be rewritten as: From Equations (28), (30) and (35), the frequencieŝ Ω * (s) can be expressed as a function of the active powers and set point frequencies,P(s) andΩ o (s), respectively, following the structural pattern: where H 1 (s) and H 2 (s) can be written as: where A(s) and B(s) are the following expressions: It should be noted that A(s) is the model of the frequency distributed averaging control. Therefore, if K c = 0, then A(s) will be I n×n and the model will be affected only by the droop method and the proposed control. Moreover, the matrix B(s) is the model of the proposed control term. Therefore, if K i = 0, then B(s) will be 0 n×n .

CONTROL DESIGN
This section presents the closed-loop model of the proposed control and a procedure to design its parameters. Figure 5 illustrates the diagram of the laboratory inverter-based islanded MG considered in this study. Figure 5(a) shows the microgrid electrical network. It is composed of four inverters represented by voltage source symbols and called VSI 1 to VSI 4. Each inverter has its DSP with drifting internal clock. The inverters are connected to the microgrid by local switches. The impedances Z 1 to Z 34 model the elements of the electrical   This study considers the dynamic phasor-based modelling approach presented in [34] because of its simplicity and accuracy. From [33], the transfer function of the inverter p i (s)∕̂i (s) =ĝ i (s) can be written as:   Table 1, being 10 mH the virtual output impedance of each inverter [27,28]. These impedances are presented in Table 2.

Closed-loop model
From Equations (41) and (42), the transfer function of the plant G i (s) can be written as: From Equation (43), the active power injection can be expressed in matrix form as: whereĜ(s) is a diagonal matrix of the local plants given by: According to the closed-loop diagram shown in Figure 6, the structural pattern (Equation 31) and the active power injection (Equation 44), the closed-loop MG model can be expressed by:

Design procedure
This subsection presents the design procedure of the new control parameter K i which correspond to the integral gain of the proposed control (Equation 18) to improve the power sharing and remove the effect due the clock drifts. The parameter K i is designed according to the dynamic specification using the closed-loop model presented in Equation (46). The design was developed from a stability analysis calculating the closed-loop poles as a function of the parameter K i . It should be done in order to place all the poles of the closedloop model in the left-hand plane. This analysis uses the system parameters listed in Tables 1 and 2 and Figure 5(b). Figure 7(a) shows the closed-loop poles sweeping K i from 0.001 to 90 mrad/s. It could be noted that the positions of the fastest poles (in black and yellow) move to the left when K i increases. Figure 7(b) shows the detailed zoom of the positions of the dominant poles. On the one hand, the pink and green poles are complex conjugates from 0.02 to 5 mrad/s. Then for K i > 5 mrad/s the pink pole moves to the left and the green pole moves to the right. On the other hand, the red and blue poles are complex conjugates moving to the right side when K i increases. Moreover, the blue and red poles are located in the right-hand plane for K i higher than 25 mrad/s, which causes the system to be unstable.
Considering the compromise between settling time and maximum deviation during transients, the value of K i is selected according to the following specifications: (i) To guarantee a good transient response with a settling time less than 5 s. (ii) To achieve a good dynamic response with low overshoots, placing the dominant poles with a damping ratio close to 0.707.
According to Figure 7, the values of K i meeting the first specification is in the range from 1.5 to 25 mrad/s. For K i > 5 mrad/s, the damping ratio of the dominant poles decreases below the desired value. Therefore, from this discussion, the value of K i selected was 4 mrad/s. This value reaches a theoretical settling time approximately of 3.50 s.

Impact of the clock drifts on system stability
To analyse the impact of the clock drifts on the system stability, Figure 8 shows the closed-loop poles with the designed gain values for different clock drift rates. Figure 8(a) shows the

Impact of the communication delays on system stability
Finally, to analyse the performance of the proposed control scheme under different communication delays, Figure 9 shows the closed-loop poles with the designed gain value for different transmission rates. Figure 9(a) shows the closed-loop poles with a transmission rate of 0.1 s. Then, in Figure 9(b) is presented the closed-loop poles for a transmission rate of 0.5 s. Finally, Figure 9(c) shows the closed-loop poles for a transmission rate of 1 s. It should be noted that the location of the closed-loop poles moves to the right when T r increases. Thus, for higher transmission rates the system may become unstable.

EXPERIMENTAL RESULTS
This section presents the experimental tests implemented in the laboratory MG shown in Figure 5. The MG is formed by four inverters working as VSIs and two loads P L1 and P L2 of 1.6 kW and 3.6 kW, respectively, each that may be connected or disconnected in the position shown in Figure 5 to form the global load P L . Each inverter was built using a 2.3-kVA Guasch MTL-CBI0060F12IXHF full bridge as the power converter and is driven by a 32-bit dual-core DSP, the Concerto-F28M36P63C with a sampling frequency of 10 kHz. This device is composed of a C28 DSP core for control purposes and a Cortex M3 ARM for communication. The communication between each VSI is based on the UDP over an ethernet link that communicate the fourth C28 cores through the M3 cores with a transmission rate of 0.1 s. The communication configuration is represented by the cyber nodes shown in the figure. Each DSP has its internal clock that differs from the others, with its own drift rates as shown in Table 1. Finally, the electrical network impedances are shown in Table 1.

Performance evaluation
First, in order to validate the performance of the proposed control scheme and the design performed in Section 4, the following experimental test was designed in the laboratory setup. The fourth VSIs start feeding a three-phase load, with a total power demand of 1.6 kW. From t = 0 s to t = 10 s the VSIs are initially driven with the conventional droop control (Equation 2). At t = 10 s the proposed control is activated. Finally, to validate the performance of the proposed control under sudden load change, at t = 20 s the second load is connected. Figure 10 shows the active powers and frequencies supplied by each inverter. It should be noted that the frequencies present a steady-state error with the conventional droop control. At t = 10 s, the proposed control is activated, and, after 3 s, the steadystate is reached with negligible error in active power, and the frequencies are rated to the nominal value. Finally, at t = 20 s the second load is connected. As usual, the step load changes cause temporal deviations in active power and frequency which are corrected once the steady-state is reached. Moreover, it should be noted that the transient response has a settling time approximately of 3 s that is similar to the desired transient response, as indicated in Section 4.
Additionally, the theoretical predictions in Section 4 are validated by the experimental results shown in Figure 11. This figure shows the active powers and frequencies of the four VSIs when using the proposed control with K i = 25 mrad/s. Note that the microgrid is unstable with this value of the integral gain. Thus corroborating the predictions made in the control parameter design analysis.

Communication delay study
In distributed systems, the communication plays an important role to achieve the control objectives. Thus, the communication parameters impact on the controller performances and therefore the dynamic of the system. It is well known that in large DG systems the DG units may be far away, this could affect in the communication services, for example, transmission delay, throughput, link failure, and so forth. Therefore, the MG performance may be compromised. In order to evaluate the performance of the proposed control scheme under communication parameters, an experimental test was designed in the laboratory setup. The test evaluates the active power sharing in response to load changes for different transmission rates. Figure 12 shows the active power and frequency of the VSIs under different transmission rates. It should be noted that the steady-state performance has not been affected by the transmission delays. However, the transient response of both Experimental results with unstable poles. The proposed control is activated at t = 10 s active power and frequency deteriorates as T r increases. This fact is predicted theoretically by Equation (46), showing that the location of the closed-loop poles moves to the right when T r increases as shown in Figure 9.

Study on communication link failures
The distributed control system relies on the availability of communications. Accordingly, communication link failures may compromise the overall control performance. Thus, to shows the performance of the proposed control to a link failure the following experimental test is designed. At the time t = 0 s the fourth VSIs were previously working with the original communication graph feeding a three-phase load, with a total power demand of 1.6 kW. Then, at time t = 10 s the communication link 2-4 has been disabled (i.e. a 24 = 0). Finally, at t = 20 s the second load is connected. Figure 13 shows the active power and frequency of the VSIs under the described link failure. It can be seen that the steady-state performance has not been affected by the communication failure. However, the dynamic responses are slower compared to the normal condition. Despite this, the proposed control is resilient to a link communication failure.

Comparative study
This subsection compares the performance of three control schemes: the local secondary control presented in [29], the droop-free control [18] and the control proposed in Equations (18) to (21). The control parameters of each policy have been defined to obtain similar dynamics among them. Moreover, the clock drift rates have been artificially magnified in order to clearly see their impact over the different control schemes. The  Table 3. Figure 14 shows the experimental results of the considered control schemes. The experimental test has the following pattern. From t = 0 s to t = 10 the VSIs are initially driven with the ). At t = 10 s the control scheme [18,29] and proposed control are activated. Finally, at t = 20 s the second load is connected. In this test, the active power and frequency errors are noticeable. In Figure 14(a), at t = 10 s, the local secondary control [29] is activated and the frequency errors are reduced. However, the deviations in active power sharing increase, with a maximum steady-state error of approximately 144 W (36% of the average power). Besides, it should be noted that after t = 20 s, at high load conditions, the deviations in active power sharing decrease. Nevertheless, the frequency errors increase. In Figure 14(b) at t = 10 s, the droop-free control is activated. It can be seen that the frequencies are rated to the nominal value after the droop-free activation. However, the droop-free control presents FIGURE 14 Performance comparison of different control schemes with magnified clock drift rates steady-state deviations in active power sharing, with a maximum steady-state error of approximately 72.5 W (18.1% of the average power). Finally, Figure 14(c) shows the proposed control performance under magnified drifting clocks. At t = 10 s, the proposed control is activated, and, after 3 s, the steady-state is reached with negligible error in active power. This result confirms the good performance of the proposed control in terms of compensation for power sharing errors, and its superiority against other control approaches in presence of clocks drifts.

CONCLUSION
A control scheme for removing steady-state active power errors in inverter-based islanded MGs has been presented. The control uses the standard droop method in the primary control layer and a combination of frequency and power control loops in the secondary layer. A dynamic analysis based on the suitable location of the closed-loop system poles has been presented, given the desired characteristics in terms of transient response and stability. The performance of the proposal control has been validated with experimental tests in a laboratory MG equipped with four VSIs each one with its DSP. The experiments demonstrated that the proposed control eliminates the steady-state errors in active power even with the presence of clock drifts in the local DSP controllers. This promising feature is valid for all load conditions. The experimental tests also demonstrated the impact of communication properties in the proposed control. In particular, the transient response worse by increasing the transmission period. Furthermore, the proposal is robust to communication link failures as long as a link is maintained between the cyber nodes. A comparison with state-of-the-art-control solutions has been presented and validated with experimental results. It was evident the superior properties of the proposal in terms of eliminating the steady-state errors in active power sharing. Finally, it is worth mentioning that the proposed power control loop can be easily included in other control policies, making the proposal relevant to solve the problem of active power sharing errors in steady-state.