Novel PLL for power converters under unbalanced and distorted grid conditions

A novel phase-locked loop (PLL) with simple structure is proposed in the present work for three-phase power converters under adverse grid conditions. Based on a synchronous rotating frame PLL (SRF-PLL), multi-resonant harmonic compensators with the ability of accommodating frequency deviations are employed in the feedback path of a pre-filter. As a result, the negative-sequence component and harmonic distortions of grid voltage can be attenuated. Different from existing methods, only classical regulators are used, avoiding complicated networks for the decoupling of unbalance and harmonics and thus greatly simplifying the control algorithm. The proposed method is analysed and designed in both the continuous s-domain and discrete z-domain, whereby stable, fast, accurate, and robust responses are achieved. Simulation results have been obtained to show the improved performance of the proposed PLL compared with two widely used methods.


Introduction
Grid synchronisation is crucial for a number of power conversion devices, e.g. grid-connected inverters, active power filters, and static synchronous compensator etc. [1,2]. In particular, gridconnected power converters form an indispensable bridge for the integration of distributed power generation and energy storage such as compressed air energy storage with power network [3][4][5]. Synchronisation with the grid is essential for the power converters to achieve proper control of the power delivered to the grid, even under adverse conditions with unbalance and harmonic distortions [6,7].
Among different synchronisation strategies such as zero crossing methods and filter algorithms, phase-locked loop (PLL) is most widely used [8]. PLLs should be able to accurately detect the phase signal of the positive sequence component of grid voltage at fundamental frequency [9]. While working in the balanced threephase grid voltage condition, a basic synchronous reference frame (SRF) PLL is able to track accuracy phase information. However, under non-ideal conditions, for example with unbalanced grid faults and/or harmonic distortions, improvements to the SRF-PLL or novel PLLs are necessary.
A number of advanced three-phase PLLs have been reported, for instance a widely used decoupled double SRF-PLL (DDSRF-PLL) [10] and dual second-order generalised integrator-based PLL (DSOGI-PLL) [11], which have demonstrated the improved performance. However, the methods are very complicated due to the decoupling units for unbalance and harmonics. A hybrid PLL with the combination of the DDSRF and a stationary frame PLL was reported to tackle unbalanced faults [12], but apparently at the expense of increased complexity. Delayed signal cancellation PLLs were proposed in [13][14][15][16], which demonstrated good harmonics filtering capability. However, a number of cascaded signal cancellation blocks are needed in order to achieve satisfactory performance. As a result, the bandwidth is severely decreased and the implementation complexity dramatically increased, and the method is sensitive to frequency deviations [14]. A decoupling strategy with a fixed sampling period sliding discrete Fourier transform and an instantaneous symmetrical components method was proposed in [17], which involved complex intricate mathematical calculations. Moving average filter-based PLLs have been designed, but the phase delay is increased and the stability is weaken which degrades transient responses [12,18,19]. Carugati et al. [20] proposed a variable sampling period filter-based PLL using the sliding Goertzel transform, which also resulted in complicated mathematical derivations. A repetitive learning-based PLL in which a Lyapunov technique was used to improve the performance was proposed in [21], but it occupied extra computation space and burden. Many other strategies such as modified SRF-based digital PLL [22], two-phase stationary frame enhanced PLL [23], and rotor PLL [24] have been reported, to name but a few. However, most of these methods are rather sophisticated in structure, which significantly increases the complexity of implementation and the computation burden of microcontrollers such as DSP and Opal-RT, increasing the possibility of time delay and overruns [25].
In order to address the limitations, a novel PLL with simple structure is proposed in the present work. Based on the SRFPLL, multi-resonant harmonic compensators [7,25] with the ability of accommodating frequency deviations are employed in the feedback path of a pre-filter stage. As a result, the negative-sequence component and harmonic distortions of grid voltage can be eliminated. Compared with those existing methods, complicated unbalance and harmonics decoupling network is not needed, which greatly simplifies the control algorithm. The proposed method is described and analysed in detail in both the continuous s-domain and discrete z-domain. Simulated results have been obtained which show the advantages of the simple but novel PLL.

Proposed PLL
The PLL proposed in the presented work is based on the SRF. The advantage in the SRF is that the fundamental positive sequence component of grid voltage can be transformed into DC signals while harmonics at two different frequencies could result in the same frequency, which facilitates the realisation of closed-loop regulators [8]. Multi-resonant harmonic compensators are employed to form a pre-filter that mitigates the negative sequence component and harmonics.

Grid voltage and transformation
Under adverse conditions, the grid voltage may be unbalanced and distorted. For the purpose of simplicity and demonstration, the voltage in the present work is assumed to contain fundamental negative sequence component and 5th and 7th balanced harmonics, given as: Eng where ω is the fundamental angular frequency, V + , V -, V 5 , and V 7 are the amplitudes of each component, and θ 1,5,7 the initial phases.
Using the Clarke and Park transformations, the grid voltage (1) is transformed into: where θ^ is the phase signal detected by the PLL. Assuming the detection is accuracy, i.e. θ^= ωt, (2) is yielded as: As can be seen, the positive sequence is transformed into DCc signals and the negative sequence into 2nd harmonics, while both the 5th and 7th harmonics become 6th order. Therefore, in order to extract clean phase signals, the 2nd and 6th harmonics should be supressed in the pre-filtering stage which will be introduced in the following.

Proposed PLL
The structure of the proposed PLL is shown in Fig. 1a, and its linearised control loop block diagram in the q-axis is given in Fig. 1b. The pre-filter is placed before a standard SRF-PLL [8]. Different from the aforementioned sophisticated PLLs with complicated pre-filters, the proposed method only employs classical regulators: a proportional integral (PI) in the forward path, and a proportional term k and resonant compensators in the feedback path. The closed-loop transfer function of the pre-filter is obtained as: 2k r ζnωs where v dq (s) = v d (s) + jv q (s), v dq ′ (s) = v d ′(s) + jv q ′(s) As can be seen, the PI is used to track the DC signals, and the resonant terms are able to supress the 2nd and 6th harmonics because of large magnitude gains at the specific frequencies [7,26].
It should be noted that resonant terms at other frequencies can be added to attenuate other order harmonics that may exist in the grid voltage. Therefore, the proposed PLL can be adjusted according to the components of grid voltage, increasing the flexibility and simplicity.

Analysis and design
In this section, the PLL is analysed and designed in both the continuous s-domain and discrete z-domain. The digital implementation in z-domain is particularly discussed to achieve frequency adaptability to avoid frequency warping. Detailed analyses of the SRF-PLL can be found in [8,10], hence it will not be discussed in the paper. The pre-filter is analysed in the following.

Analysis in the s-domain
Bode diagrams of the open-loop transfer function, with and without the resonant terms, are shown in Fig. 2. It is apparent that the resonant terms only influence the response at the resonant frequencies by introducing abrupt magnitude ripples and ± 90°p hase jumps. Furthermore, the phase responses never cross −180°; therefore, the system is always stable even with the insertion of other resonant terms at higher harmonic frequencies [25,27]. Therefore, sufficient large k p and k i can be used so that the closedloop transfer function (4) in steady state can be approximated as: In order to achieve zero steady-state error in tracking the dand q-axes voltages, k should be 1.
Closed-loop pole-zero maps, with fixed k r and ξ and different values of k p and k i , are shown Fig. 3. It can be seen that the PI has a negligible influence on the position of the poles. Thus, the transient responses are mainly determined by the resonant terms. k p = 100 and k i = 500 are used in this case.
Regarding the resonant terms in the pre-filter, the gain k r should be a large value to gain a high attenuation of harmonics, whereas the damping factor ξ should be low so that a low bandwidth is obtained to achieve effective harmonic compensation [7]. The step responses of the pre-filter with different values of k r and ξ are illustrated in Fig. 4. k r = 1000 and ξ = 0.0005 are chosen to obtain a fast and relatively smooth response.

Implementation in the z-domain
In order to implement the proposed method in a digital controller such as DSP, the PLL needs to be discretised. The PI controller can be discretised using the Tustin's method [2]. With respect to the resonant terms, the Tustin's method with pre-warping is adopted to avoid frequency warping and thus to effectively eliminate the harmonics, by replacing the Laplace variable 's' with [25] s = nω tan(0.5nωT s ) As a result, the resonant terms are discretised to To make the PLL frequency adaptive, the resonant terms are implemented as Fig. 5, where ω′ is the angular frequency detected by the PLL (see Fig. 1), x(z) denotes the input and y(z) the output. The resultant closed-loop Bode diagram is shown in Fig. 6 (a sampling frequency of 10 kHz is used). It is obvious that the pre-filter is able to accurately track DC signals with zero steady-state error and successfully mitigate the harmonics without frequency warping.

Results
Simulations in Matlab/Simulink have been carried out to validate the proposed PLL and also to verify the advantages over two widely used method: DDSRF-PLL [10] and DSOGIPLL [11] which contains complicated decoupling units for unbalance and harmonics. The 5th and 7th harmonics decoupling units are included in the DSOGI-PLL according to the design in [11]. Identical SRF-PLL has been used in these three strategies for a fair comparison.
In the first scenario, the fundamental frequency is fixed at 50 Hz. The amplitude of single-phase grid voltage is set to 155 V. At the first 0.15 s period, the grid voltage is balanced, from 0.15 s the A-phase voltage amplitude is decreased to 100 V, from 0.225 s 5th (V 5 = 15, θ 5 = -25°) and 7th (V 7 = 10, θ 7 = 35°) harmonics are added to the grid voltage. The results are demonstrated in Fig. 7. It can be seen that the DSOGI-PLL has a relatively slow response in tracking the frequency and fundamental positive sequence d-axis voltage ( = V + ) although the dynamic error in tracking the fundamental positive sequence q-axis voltage is ignorable, while the DDSRF-PLL is able to resist the unbalance but fails to mitigate the harmonics. By comparison, the proposed PLL is able to accurately and quickly extract clean positive-sequence signals.
In the second scenario, the frequency adaptive capability is tested. The grid voltage in this case consists of a fundamental positive-sequence (V + = 155) and negative-sequence (V -= 50, θ 1 = 0°), the fundamental frequency is changed from 50 to 45 Hz at 0.15 s. The results are presented in Fig. 8. Both the proposed method and DDSRF-PLL can fast and accurately detect the signals of the positive-sequence component, even when the grid frequency deviates from its nominal value. The DSOGI-PLL, on the other hand, generates significant fluctuations in the frequency and d-axis voltage signals. As a matter of fact, it takes more than 1 s for the DSOGI-PLL to achieve zero steady-state error. Therefore, the robustness of the DSOGI-PLL against frequency deviations is proved to be very weak.  The simulated results confirm the advantages of the proposed PLL. In brief, the DDSRF-PLL is sensitive to harmonic distortions and the DSOGI-PLL has slow dynamic response leading to a weak robustness against frequency deviations. The proposed PLL, with a much simpler structure, is immune to grid unbalance and harmonics and at the same time is adaptive to frequency drifts with fast response.

Conclusion
Here, a novel PLL has been proposed for three-phase power converters under unbalanced and distorted grid conditions. Based on the SRF-PLL, a pre-filtering stage with multi-resonant harmonic compensators has been designed. The method is analysed and tuned in both the continuous s-domain and discrete z-domain. In particular, the digital implementation in z-domain has been discussed in order to avoid frequency warping. In comparison with existing methods, the proposed PLL is frequency adaptive and is able to fast and accurately detect clean phase signals with significantly reduced control complexity and computation burden due to its simpler structure. The advantages of the proposed strategy have been validated by simulated results in different scenarios.