A high frequency current source converter for a direct drive powertrain in a wave energy converter

Wave Energy converters (WECs) generally use a mechanical solution such as hydraulics or gearing to optimise the extraction of energy from the incoming waves prior to converting it into electrical energy via a high speed rotating generator. This simplifies the Electrical Power Conversion System (EPCS) design and facilitates the use of mechanical energy storage such as springs, compressed air or hydraulic accumulators. The naturally peaky nature of the WEC power can thus be reduced and there is potential to tune the resonant frequency of the WEC [1]. The potential design of a Current Source Converter (CSC) for an integrated low-speed direct-drive Power Take-Off (PTO) for a WEC is described here. Silicon Carbide (SiC) devices which enable high switching frequencies with a beneficial reduction in passive component dimensions are considered. Issues such as fault tolerance, protection and parasitic inductance are investigated leading to an improved layout proposal.


Introduction
Defining the functional requirements for a WEC PTO is not straightforward.The range of variables include: wave resource, location, device type, structure, mooring, PTO components and control methodology.To overcome this issue a generic WEC based on a point absorber WEC and PTO model has been developed as a 25kW WEC case study for this project [2].The WEC has a 10 module linear generator, each module having an associated EPCS rated to supply the combination of mechanical reactive power needed to tune the WEC and any electrical reactive power for the generator whilst extracting the maximum available energy from the incoming waves [3].In this case, the converter kVA rating is 10x the generator maximum average power rating of the module.The general arrangement for a three module PTO is illustrated in Figure 1.In a direct-drive solution, it is recognised that a local Energy Storage System (ESS) will be required and supercapacitors are considered the most likely candidate to achieve this, although the technology is still evolving [4,5].Adopting a CSC topology is one possible approach to reduce the converter capacitance.In a Voltage Source Converter (VSC), capacitors are considered to be a significant source of failures [6].For a traditional low frequency CSC, the DC link inductor is a significant cost element which also impacts the efficiency and dictates the overall dimensions of the converter.As a result, the CSC is typically restricted to multi-MW drives where it can advantageously utilise slow switching, high power devices with low conduction losses [7].Recently, interest in applying wide bandgap devices to enable low-loss, high switching frequency variants of the CSC have been reported [8,9].These new variants offer potential advantages in terms of increased robustness, reduced inductor size as well as improved operating efficiency.Assessing the suitability of a high switching frequency CSC for a WEC application is the basis of this investigation.By way of an example, a comparison of size and cost of three commercially available DC-Link inductors quoted for the prototype CSC are presented in Table 1.  1 : Impact of switching frequency on the DC link inductor parameters The higher frequency inductor increases complexity; requiring the use of low-loss magnetic cores and mitigation of increased winding losses due to skin effect, such as by the use of foil windings etc.This paper is organised as follows: The operation of a 10kHz switching frequency CSC on the case study WEC is presented in section 2. Section 3 describes the investigational steps taken towards achieving a switching frequency of 100kHz, followed by a discussion and conclusion in section 4.

CSC operation on a WEC
The basic topology of the generator CSC interface with an ESS current to voltage source DC-DC converter for one module of the PTO is shown in Figure 2. A Voltage Source Converter (VSC) and separate DC-DC converter would typically be considered for this application, however, in addition to the DC-link capacitors for the VSC, the DC-DC conversion stage would require its own inductor to facilitate the buck/boost functionality necessary to match the generator output to the required DC-link voltage and enable the ESS voltage to vary as energy is stored and retrieved.In a WEC application, with the continuously pulsating power flow, a CSC is well suited as the DC-Link inductor is inherently robust and able to cope with the cyclical power flux.The combination of the CSC and the DC-DC interface, illustrated in Figure 2, allows for charging and discharging the ESS and can boost the ESS voltage as required to match the generator voltage.Previous investigators have demonstrated the suitability of this topology for an electric vehicle inverter application [10].A three-phase CSC and DC-DC model, developed in PLECS ® incorporating Space-Vector (SV) modulation techniques and a switching frequency of 10kHz verified the suitability of the CSC and DC-DC topology for this application.The SV modulation minimises switching transitions and control of the CSC is arranged to ensure the sinusoidal current in each phase is either inphase with the back-emf of the generator for motoring or 180 degrees out-of-phase for generating.In this way full four-quadrant control of the Vernier Hybrid Linear Machine (VHLM) generator for the WEC is achieved.At its simplest, the magnitude of the three-phase currents can be controlled by modulating the DC-Link current to suit the peak current demand from the generator with the modulation index held at 100%.This approach maximises the CSC efficiency.For improved dynamic response, the modulation index can be adjusted to suit the phase current demand, but the efficiency of the converter will suffer in this mode [7]. Figure 3 shows that the CSC current and voltage waveforms to the generator with AC output filter capacitors of 20µF and a DC-link inductor of 10mH.
For the E-drive 25kW PTO, it is envisaged that the complete VLHM linear generator would comprise ten individual 2.5kW segments, each with their own CSC.The VHLM in this initial model has a power factor of 0.2 and efficiency of 0.9 which are typical [11].The impact of the generator efficiency and low power factor on converter kVA rating combined with the mechanical reactive power needed to tune the WEC when the wave frequency is not coincident with the WEC natural frequency is  4. Here, the module CSC draw is 7kVA for an average output power of 2.5kW at a wave period, T, of 7.25s increasing to 8kVA for an average output power of just 1kW at T=6.25s.The energy storage requirements are predicted by integrating the difference between generator instantaneous power flow and the average real power from the CSC that would be passed to the grid.In this case, the pk-pk storage requirement increases with reactive power control from 3.22kJ at T=7.25s to 4.15kJ at T=6.25s.Improvements to the generator have been made by the machine design team on this project leading to a higher power factor of the prototype VHLM machine of 0.5.This has been achieved by increasing the magnet mass and geometry [12].

High frequency switching
From Table 1, it is evident that increasing the switching frequency from 10kHz to 100kHz reduces the energy storage requirement of the DC Link inductor and hence the volume and cost.A reduction in passive component energy storage requirement applies for both the VSC and the CSC with increased switching frequency and in both cases, issues such as switching losses, parasitic inductances and gate drive requirements become more challenging at these higher switching frequencies.In the case of the VSC, there is a wealth of published work, but rather less in the case of the CSC/CSI [8,9].Perhaps one of the major drawbacks of the CSC or CSI topology is the requirement for a switching device with reverse blocking capability.The series combination of a diode and MOSFET or IGBT is the obvious solution, but always results in increased onstate losses.Reverse Blocking IGBTS (RB-IGBT)s based on Silicon (Si) technology have been promoted by certain manufacturers, offering relatively low on-state loss, but typically the switching losses can be quite high and when combined with significant diode reverse recovery current, the maximum switching frequency is limited.Further, there are very few products commercially available at this time.The combination of a Silicon Carbide (SiC) MOSFET and SiC Junction Barrier Schottky (JBS) diode, ideally in a custom module, is reported to provide the best compromise in hard switching applications [13].SiC devices, both diodes and MOSFETS, are relatively recent additions to the gamut of commercially available power devices and have yet to reach maturity compared to Si devices.Existing SiC devices can achieve both low switching loss and low conduction loss for a wide range of blocking voltages and frequencies, albeit at a higher cost/watt than an equivalent Si device [14].

100kHz switching operation
Fundamentally, there is no impediment to operating the CSC at 100kHz switching frequency.However, the validation simulation assumes that the commutation capacitors, DC-link inductor and devices are ideal and that there are no significant stray inductances or capacitances within the circuit.Figure 5 (a) illustrates this ideal converter operating for the laboratory prototype generator, rated for 1.1kW.Practical challenges relate to high frequency current sensing, control, thermal performance of the switching devices and assessing the impact of stray inductance or capacitances.
Using the manufacturer's supplied models, the thermal performance at rated conditions for the selected devices can been modelled to establish a baseline as illustrated in Figure 5 (b).Here, SICD1 is the SiC series diode and FET1 is the SiC FET within device 1 of the CSC.In this ideal circuit, the FED antiparallel diode is not required.The CSC heatsink loss shown is the combined losses from all six devices and for the chosen heatsink with an ambient temperature of 35 degC.There is a significant safety margin with this particular combination as the modelling takes no account of secondary effects and assumes ideal switching.During commissioning, should it become necessary to slow the devices down to reduce ringing and overshoots, the switching losses will increase, also an allowance for operational overload is helpful.

Protection
Control or device failures during operation will create dangerously high voltages in the CSC.For example, should all the devices inadvertently switch off before the DC-Link is discharged, the waveforms of Figure 6  Metal Oxide Varistors (MOV) are insufficiently rapid to protect the DC link, but can be used effectively in conjunction with the commutation capacitors to protect against overvoltage in the generator windings.A contactor is required to extinguish the current flow from the generator into the commutating capacitors thereafter.Other more complex strategies exist for protecting the DC link inductor, the problem being the extremely high dv/dt during faults [15].One potential advantage of adopting high frequency switching is that the stored energy in the inductor is significantly reduced and Transient Voltage Suppression (TVS) diodes are capable of limiting the over voltage and also handle the expected stored energy as shown in Figure 7: source-drain inductance, the diode inductance and any wiring self-inductance etc in the converter leg.In the commutation capacitor, Lpar will be the capacitor equivalent series inductance and any wiring self-inductance in the capacitor interconnections to the relevant converter legs.For simplicity, each Lpar is assumed equal in this initial assessment in series with a nominal damping resistance.A further consideration within the CSC is the peak current flow during commutation due to charging and discharging junction capacitances in the switching devices.Ironically, the parasitic inductance will act to limit the di/dt during commutation and in doing so limit the peak reverse recovery current.Hence, the peak current flow as the diode switches off and the peak overvoltage across devices are the factors of most interest in assessing the design limits.
Figure 8 : CSC Commutation test circuit A CSC parasitic evaluation simulation has been set up, Figure 8.The DC link current is controlled by a proportional controller driving an ideal voltage source connected to the DCV+/-terminals.To observe the high frequency commutation effects, the devices are programmed to switch between two distinct 100kHz PWM patterns designed to charge and discharge the commutation capacitor over 1.4ms reproducing system peak voltages and currents in the load resistor.The device models are set up to reflect limited di/dt, during switching, internal capacitances and reverse recovery as provided from the device datasheets.

Layout consideration
Laminar busbars are a well-known approach for minimising self-inductance in power electronics.They rely on thin, wide flat conductors to minimise self-inductance and skin effect.When two such conductors are mutually coupled with a minimal air gap and balanced, opposing current flow the effective self-inductance is further reduced [16].In the CSC, with delta connected commutation capacitors it is conceptually difficult to quantify with any confidence the self-inductance due to mutual coupling that will be seen during each transition in the commutation sequence.One option is to select a specific layout and apply Finite Element Analysis (FEA) modelling to predict the partial inductances for each switching state and change in physical variables such a layer number or device position [17].More usually, rules of thumb are applied, such as reducing loop lengths and building a prototype.Parasitic parameters can then be estimated by monitoring the overvoltage during switching transients.The FEA approach is well suited to making incremental improvements or validating an existing design, but the shear range of variables involved in the prototype stage, such as optimal choice of capacitors, heat sinks, power devices makes it very difficult to apply in any general way.Results are potentially error prone due to incorrect assumptions with effects such as proximity, skin effect and mounted components.
With SV control, an example of the device switching is shown in Figure 11 for a typical PWM cycle.One device will be energised for the full PWM period, either top or bottom leg, and the desired magnitude of the current vector will be defined by the duration of the  ⃗ 2 ,  ⃗ 0 &  ⃗ 1 switching patterns for the three devices in the opposing legs.In the CSC, there must always be a viable current path which requires an overlap between switching states to be applied, similar to the dead-time required in a VSC.
Based on the guidelines presented in [16], the following layout has been identified as a preliminary candidate for the prototype CSC.The layout is based on maximising the use of balanced currents where possible within laminar busbar structures as illustrated in Figure 12, Figure 13 & Figure 14.

Discussion and Conclusion
The work concludes that a CSC and DC-DC converter can be applied to provide a four quadrant generator interface for a WEC.
In an effort to reduce the volume of the interface, SiC devices and a high switching frequency is proposed.That brings with it other challenges, not least of which is accurately monitoring high voltage, high bandwidth voltage and current waveforms during testing and for control.This paper has highlighted steps taken to foresee, quantify, and where possible, overcome challenges to developing a high switching frequency CSC for this project.Recent effort has focused on minimising the self-inductance of the CSC layout and interfacing key components such as the commutation capacitors.As yet, no simple method for reasonably quantifying and comparing the loop-inductance in significantly different layouts and components has been identified.This is partially due to the low levels of self-inductance being sought where even adding quite small features such as a connection tab, via or mismatch between coupled layers can add several nH to the loop self-inductance.Working formulae presented in [16] and elsewhere are insufficiently accurate or make simplifying assumptions such as balanced current flow and FEA is rather time consuming for quick evaluations.Achieving self-inductance equality between each to the three phases for each switching event is desirable, but also likely to be difficult due to the structural variation between the phases.By observation of the switching states, one possible layout has been identified.The dimensions of which will be governed by the physical connections to the switching devices and passive components.It has been concluded that adopting best practice rules of thumb and "just trying it" is going to be the next step and work is ongoing.

Figure 2 :
Figure 2 : Proposed CSC topology with ESS interface

Figure 7 :
Figure 7 : Impact of control failure, with protection in place.(a) Generator interface (b) DC link

Figure 9 : 7 Figure 10 :
Figure 9 : Example with Lpar = 50nH (a) System variables (b) Device variablesFor a value of Lpar of 50nH, typical waveforms for one PWM cycle are shown in Figure9.It is interesting to note that the model now predicts that the FET antiparallel diode conducts current during the switching transitions due to reverse recovery current flow from the series diode.Figure10demonstrates the sensitivity of the converter to a range of values of Lpar with SiC series diodes.The model predicts that a value of Lpar less than 50nH will result in excessive current spikes during commutation and for Lpar greater than 200nH will result in device overvoltage.This suggests total self-inductance in any leg must lie between 150uH and 600nH.