New modulation scheme for bidirectional qZS modular multi-level converters

: This study proposes a dedicated modulation scheme for a bidirectional quasi-Z-source (qZS) modular multi-level converter. The operation principle and a suitable pulse-width modulation method are proposed. The relation between the modulation index and shoot-through duty ratio is derived. A formula for calculating the required value of qZS capacitance is given. The simulation results presented in the study validate the operation and the performance of the proposed topology.


Introduction
Multi-level inverters (MLIs) are preferred due to their attractive features compared with two-level voltage source inverters (VSIs) [1] such as better AC voltage quality, low voltage stress on semiconductors, possibility to produce significantly higher voltages than a single-switch voltage rating. The modular multi-level converter (MMC) is a relatively new competitive concept which has been proposed in 2002 [2]. It provides several features such as modularity, voltage, and power scalability and failure management capability in the case of device failures [3]. These advantages favour the MMC for various applications, such as an interface between high-voltage direct current (HVDC) [4] and flexible AC transmission (FACT) systems [5], driving medium-voltage (MV) motors [3], and connecting renewable energy sources such as photovoltaics [6] and wind energy system [7] to MV grids. The output voltage of most renewable energy sources fluctuates with working conditions; therefore, having a converter that can adapt to these fluctuation by being able not only to step down but also to step up the voltage in order to regulate the voltage at the DC-link terminals may be quite useful. Power converter topologies based on the use of the impedance network concept have been proposed in [8] which proposes the implementation of a quasi-Z-source (qZS) MMC. The basic structure of the quasi-Z-source inverter (qZSI) as proposed in [9] is shown in Fig. 1. The operating principle of the qZS network relies on producing a short circuit (shoot through, ST) at inverter DC-link terminals in order to increase the stored energy in the inductors that is later transferred in the qZS capacitors and, finally, this extra voltage adds up to the DC source voltage and provides voltage boosting capability.
There are two operation modes for the qZS network which are ST and non-ST (NST) modes. In the ST mode, the DC-link terminals are shorted by gating both the upper and lower devices of at least one inverter leg, which forces the qZS diode D to become reverse biased and therefore behave like an open circuit as shown in Fig. 2a. Hence, the stored energy in the capacitors begins to transfer into the inductors. In the NST mode, the inverter operates by producing active and null voltage states [10] and then D will be forward biased as shown in Fig. 2b; the stored energy in the inductors begins to transfer to the load, which sees V po = V c1 + V c2 as its DC-link voltage, and qZS capacitors begin to charge.
Khera et al. [8] proposed the integration of the qZS network with a single-phase MMC to provide voltage boost capability. The proposed circuit faces some limitations which were identified in the same paper, and a solution was proposed by modifying the qZS-MMC to be a bidirectional one (BqZS-MMC).
This paper gives a detailed circuit analysis of the proposed BqZS-MMC. The equivalent circuit of the qZS-MMC with the proper implemented sinusoidal pulse-width modulation (SPWM) boosting scheme is presented which can be extended to any number of output voltage levels. The relation between the modulation index and ST duty ratio for any number of voltage levels is derived. A guideline for choosing the value of qZS capacitance is proposed. Finally, the operation and analysis of the proposed modulation scheme are validated using results simulation from a MATLAB/PLECS model.

Operation principles of the bidirectional quasi-Z-source modular multi-level converter
The topology of a single-phase qZS-MMC is shown in Fig. 3. The MMC leg consists of the upper and lower arms where each arm consists of series-connected sub-modules (SMs), and an arm inductor (L o ). Each SM has a half-bridge inverter configuration with one DC-link capacitor. The two switches (S a and S ax ) in SM are controlled by complementary gating signals. When S a is on, the SM capacitor is bypassed and the SM terminal voltage is zero. If S a is off, S ax is on; therefore, SM terminal voltage is V c and the SM capacitor is inserted into the circuit. Each SM capacitor needs to be charged by a fraction of the DC bus voltage E/N, where N is the number of SMs per arm. Therefore, the output voltage (V ao ) swings between -V pn /2 and V pn /2 and each arm should aim to produce the reference output voltage potential, as average over one switching period. Output inductors L o have the role to limit the current ripple caused by the momentary mismatch of voltage produced by the two arms, and also enable the control of circulating current needed to replenish the energy in the SM capacitors. The modulation scheme for generating these states will be explained in Section 4.
The output voltage equation as a function of the upper arm, lower arm, and the DC-link voltages is given by From (1), if the upper qZS network is shorted via S u , i.e. v po = 0, the upper arm voltage v pa should be reduced to keep the required output voltage at a certain level which can be achieved by reducing the number of inserted cells in the upper arm by N/2. The same procedure is followed if the lower qZS network is shorted via S n . In this study, phase disposition SPWM (PD-SPWM) is used to control the MMC arms [11]. S u and S n have been modulated using the proposed technique as follows.

Capacitor voltage balance
MMC requires a voltage balancing strategy to balance and keep the SM capacitor voltages at their desired average values. The implementation of balancing strategies depends on the presence of the redundant states in the MMC arm [10]. The redundant switching state with the strongest effect in facilitating voltage balancing is always selected. The MMC arm capacitor balancing can be achieved by different strategies [10]. The most widely used balancing strategy is based on the sorting method [6] which is summarised in four steps as follows: (1) Measure and sort the upper and lower capacitor voltages.
(2) From modulation scheme, determine the number of inserted cells (n p and n n ) from the upper and lower arms, respectively.
(3) If the upper (lower) arm current is positive where the current direction as shown in Fig. 3 is considered as positive, choose the n p (n n ) cells with a lower voltage to be inserted. Therefore, the corresponding cell capacitor is charged and its voltage increases.
(4) If the upper (lower) arm current is negative, choose the n p (n n ) cell with a higher voltage to be inserted. Therefore, the corresponding cell capacitor is discharged and its voltage decreases.

Modulation scheme
To synthesise n-level voltage waveform at the converter AC side where n equal 2N − 1, phase disposition SPWM (PD-SPWM) with two complementary reference signals (v mn and v mu ) is used in this study to control the BqZS-MMC as indicated in Fig. 4. Each carrier is responsible for producing the gating signals of two cells (one from upper and one from lower arm). The reference signals are compared against the carriers to define which leg switches are conducting. The upper (lower) qZS networks can be in the ST mode if the number of upper (lower) inserted cells equals or is higher than N/2. Therefore, the number of inserted cells can be reduced by N/2 to obtain the required voltage level. According to this concept, this modulation scheme can be named as the reduced number of the inserted cell (RNIC) technique. By considering N = 4, the number of output voltage level will be 9 as clarified in Fig. 4. Table 1 lists the available voltage levels when N = 4 by clarifying the number of inserted SMs in both the upper and lower arms for each level before and after introducing ST intervals and which qZS-network switches S u and S n should be gated. Su can be shorted during all output voltage levels except levels 1, 2, and 3 (7, 8, and 9 for S n ) as shown in Table 1 and Fig. 4, because at these levels, the number of inserted cells from the upper (lower) arm is <2 (N/2). Therefore, ST signals of S u at levels 1, 2, and 3 are set to zero. Fig. 4 shows the output voltage waveform, ST signals, and the gating signals for both S u and S n . The upper ST signal (V sh-u ) is defined by where M sh is the ST modulating signal height as shown in Fig. 4. In the range from ϴ1 to π−ϴ 1 , the number of inserted SMs per arm became lower than N/2, where the ST interval should set at zero, and ϴ1 is defined by The lower ST signal V sh-n waveform is of the same shape as V sh_u but shifted by 180° as shown in Fig. 4. The pulses of S u and S n are generated if the carrier signal C sh is higher than V sh_u and Vsh-n, respectively. According to V sh_u and V sh-n signals, the output voltage reference waveforms (V mu and V mn ) for the upper and lower arms are modified as shown in Fig. 5 in order to provide a reduction in the number of inserted cells during these intervals by two cells (N/2). From (2), the instantaneous value of the duty ratio is given by By integrating (4), the average ST duty ratio D sh can be calculated which is given by D sh = (π + 2θ 2 )(1 − M sh )/2π + (θ 1 − θ 2 )/π + NM sh (cos θ 1 − cos θ 2 )/π From (5), The DC-link voltage can be expressed by For N of SMs per arms, the SM capacitor voltages are given by From (8), the peak value of the fundamental output voltage is given by Where G is given as a function of D sh (or M sh ) and the output voltage modulation index M is given by

Choosing values of a passive element
According to [8], using an IGBT in antiparallel to the diode D in the BqZS-network allows the converter to operate with small values of inductance without disturbing the operation of the circuit, being able to completely avoid the undesirable operation modes found in [8], consequently, eliminating any drops in the DC-link voltages that affected the output harmonic distortion. However, the qZS-inductance value should be chosen for limiting the ripples to a reasonable level (20%) to reduce the current stress on the converter devices.
The inductance value of the four inductors is chosen according to [12]. The arm inductance and SM capacitance are calculated according to the relevant study and the relations given in [13]. In this section, the general relation for determining the proper qZScapacitance value has been obtained. According to [8], the qZScapacitor voltages V cu1 and V cu2 (V cn1 and V cn2 ) decrease when the arm current value i pa (i na ) is higher than the average value of the inductor current IL during both ST and NST modes as indicated in Fig. 7. The interval when the arm current is higher than the average inductor current ranges between θ a and θ b , where θ a and θ b are the two instants when the arm current is equal to I L . The upper and lower arm currents can be expressed by i pa = i a /2 + i 2 f + I dc ; i na = − i a /2 + i 2 f + I dc (11) where I dc is the DC component in arm currents which is responsible for transferring real active power from the supply to the load. The i 2f is the second-order harmonic usually present in any single-phase converters and i a is the AC load current component. In the following analysis, the value of the second-order harmonic is not a significant as ia, so i2f is not considered and set to zero in (11). From the power balance equation, the maximum value of the load current I a can be calculated by where Ф is the load displacement angle, I dc is the DC component in the arm current which can be calculated as a function of the average value of the qZS-inductor current by Substituting (12) and (13) into (11), and equating the resultant equation by I L , θ a , and θ b can be calculated by The capacitance C u1 can be obtained by According to Fig. 7, Δt and Δv cu1 can be defined as where V cu1 is the average value of the qZS capacitor voltage, k V is the ratio between peak-to-peak capacitor voltage Δv cu1 and V cu1 , and f o is the output load frequency. The capacitor current I c during the interval from θ a to θ b is given by The average value of i c (t) over a switching period is given by Substituting (11)-(13) into (18), and integrating from θ a to θ b , the average value of i c over the interval from θ a to θ b is given by Substituting (7) and (19) into (15), the minimum required capacitance to provide a k v voltage ripple can be obtained as

Simulation results
To verify the validity of the proposed modulation scheme for the BqZS-MMC, a simulation model is implemented in MATLAB/ PLECS for the proposed configuration shown in Fig. 2 with a number of SMs equal to 6. The parameters used in the simulation models are given in Table 2. The simulation study has been carried out using a passive (R + L) load and considering that all system components and switches are ideal. The optimum qZS-capacitors (C u1 and C n1 ) were calculated in order to provide the voltage ripple factor kv of ∼10%. Based on the parameters in Table 2, the required value of the qZS capacitor is ∼3.15 mF which is calculated by (20).
The converter modulation index M is set at 1 and the ST modulation index M sh is set to 0.8 (boost), 0.6 (boost), and 1, (buck) and consequently the ST duty ratio D sh is equal 0.124, 0.256, and zero, respectively. Figs. 8 and 9 show the upper, lower, and overall DC-link voltage, and their zooming. By lowering M sh from 0.8 to 0.6, the peak value of the overall DC-link voltage is increased from 4 to 6.2 kV. Also, to check the operation in the buck mode, Msh is set at 1, where the peak value of the overall DC-link voltage becomes 3 kV that is equal to the DC source voltage E.
The simulation results of the qZS-network capacitor (V cu1 , V cn1 , V cu2 , and V cn2 ) and arm capacitor voltages are shown in Fig. 10, and Fig. 11 illustrates their zooming. These capacitors are charged according to the relations given in (7) and (8). The ripple factor k v  of V cu1 and V cn1 is ∼10% which confirm the validity of the proposed capacitance formula. Load voltage and current are shown in Fig. 12. For the proposed BqZS-MMC, by lowering M sh from 0.8 to 0.6, the peak value of the output voltage fundamental component is increased from 2 to 3.1 kV. However, for traditional MMC, the peak value of the output voltage is limited to the halfvalue of the supply voltage (E/2 = 1500 V). The output current shown in Fig. 12 does not show low-order harmonics, which is a sign that the proposed modulation works as expected.

Conclusion
This paper proposed a modulation scheme for a bidirectional qZS MMC topology that is able to achieve buck and boost voltage capabilities. The relation between the modulation index and average ST duty ratio has been derived and verified by simulation at different modulation indices in both the buck and boost modes. An analytical design methodology for calculating the required values of qZS capacitors has been proposed, and the resulting ripples in the simulation match the ripple imposed in the design.