7L-SCBI topology with minimal semiconductor device count

: In this work, a seven-level switched capacitor boost inverter (7L-SCBI) is proposed with minimal resource count. The proposed inverter requires only eight switches and two capacitors to generate a seven-level voltage. The proposed 7L-SCBI is capable of generating a multilevel voltage as well as boost the input DC-link voltage up to 1.5 times with a reduced blocking voltage of switches and capacitors. The comparison in terms of efficiency and device count with other switched capacitor topologies is presented in detail. The performance validation of the proposed 7L-SCBI is done with the help of a laboratory prototype.


Introduction
In high-power and high-voltage applications, the multilevel inverters (MLIs) are gaining remarkable interest in the industry as well as academia from the last three decades over two-level inverters. The MLIs have numerous advantages such as reduced dv/dt stress of the switches; improved power quality of the output voltages w.r.t. increased number of levels and minimised harmonic profile; reduced filter requirement; lower Electromagnetic interference (EMI) issues; minimised common-mode voltages etc. [1][2][3]. The renowned existing MLI configurations are namely, cascaded H-bridge (CHB), neutral point clamped (NPC), flying capacitor clamped (FCC), dual inverter (DI) and T-type-based MLIs. Even though these MLIs have several advantages, however they also have limitations of device count as the number of levels increases (number of switches, diodes, capacitors, isolated DC sources), in addition to capacitor balancing issues [1][2][3].
In [3], numerous hybrid topologies such as CHB topology with floating capacitors, active NPC, hybrid topologies with a combination of either NPC with CHB or FCC with CHB, packed U-cell etc. are discussed. However, the device count and output voltage gain are the major limitations with most of the topologies. A five-level MLI with switch boost capability is proposed in [4], where nine switches were used to attain the output voltage gain of 2. In [5], another five-level inverter topology is presented with ten switches and four capacitors; however, no additional gain is achieved. In these topologies [4,5], the flying capacitor concepts with the combination of CHB circuits have been used, resultantly, these circuits require a higher number of devices. A new family of seven-level switched boost topologies has been presented in [6], with the help of CHB and T-type MLI concepts. However, this configuration requires four capacitors for clamping the DC-link voltage and for boosting the voltage to 1.5 times, ten switches were required.
Several seven-level inverter topologies have been presented in [7][8][9][10][11], where a higher number of switching devices as well as capacitors have been used, which makes the system costly. Some topologies achieving a higher number of voltage levels have also been proposed in [12][13][14]. However, these topologies suffer from higher voltage ratings of components. To overcome these issues, there is a necessity to implement an optimal seven-level configuration with a minimal number of switching devices and capacitors, meanwhile achieving a boost of the applied voltage. In this paper, a seven-level switched capacitor boost inverter (7L-SCBI) topology is proposed using only eight switches. The proposed 7L-SCBI requires only one DC source (with a magnitude of V dc ) and two capacitors for achieving a voltage boosting capability of 1.5.

Proposed 7L-SCBI and analysis
The proposed 7L-SCBI configuration is represented in Fig. 1a. In the proposed inverter, capacitors C 1 and C 2 are used effectively to boost up the DC input voltage as well as for clamping the DC-link voltage into two equal magnitudes. The two-switch inverter legs connected to the DC link will generate 0, V dc , -V dc voltage levels and the capacitors branch along with clamping switches will generate V dc /2, -V dc /2, V dc , −V dc . As a result, the proposed 7L-SCBI is able to generate a 7L voltage across the load terminals (A and B). Conclusively, the levels 3V dc /2, V dc , V dc /2, 0V, −V dc /2, −V dc , −3V dc /2 are achieved here. The equivalent circuit for all the possible switching states for generating the 7L voltages across the load terminals A and B is shown in Figs. 1b, 2 and 3 as well as in Table 1.
The capacitors C 1 and C 2 are charged to V dc /2 voltage equally by connecting this combination in parallel with the DC input source during the states of 0, V dc , −V dc levels. Due to the higher number of switching state redundancies of the proposed 7L-SCBI, the charging of capacitors can also be done by connecting the individual capacitors in series with the DC source and load, i.e. C 1 is charged during -V dc /2 level and C 2 is charged during +V dc /2 level. From the switching Table 1 and Figs. 1-3, it can be observed that the capacitors are charged and discharged symmetrically which ensures that the capacitors are self-balanced. From Table 1, it can be observed that +V dc /2 and −V dc /2 voltage levels have a higher number of switching redundancies, which help in achieving the capacitor voltage balancing under disturbances or unbalanced conditions.

Determination of capacitance value
The selection of capacitance value for any capacitor has a significant role in the switched capacitor-based MLI topologies. In the proposed topology, only one capacitor is used in a one halfcycle, which gives a better voltage profile. The ratings of switched capacitors used in the MLI topologies are mainly depending on the capacitor voltage ripple, i.e. ΔV c . Fig. 4 shows the output voltage along with the capacitor voltages when the carrier signals are replaced by a constant line. As depicted in Fig. 4, the maximum discharging time for capacitor C 1 is t 3 to t 3 ′. The capacitor C 2 is not    discharged during the positive half-cycle. During the negative halfcycle, the capacitor C 2 is discharged and the voltage of the capacitor C 1 does not change. Therefore, based on capacitor ripple voltage, the value of capacitance is given as where I pk is the peak load current and f o is the output voltage frequency.

Modulation strategy
The proposed topology is modulated with the level-shifted pulse width modulation (LS-PWM) technique. In this LS-PWM for generating a seven-level voltage, six carrier signals (of magnitudes V c ) are compared with the sinusoidal reference signal as shown in Fig. 5. The control logic for different switches present in the proposed topology is generated according to the switching logic given in Tables 1 and 2.

Comparative study
To prove the superiority of the proposed inverter, a detailed comparative study of this inverter is done with other existing conventional inverters in terms of the number of devices, voltage stresses and other parameters for the different 7L topologies. Table 3 gives a detailed device comparison of the different SCBI topologies when compared to the proposed topology. Similar to the proposed MLI configuration, the topologies in [6,7,[9][10][11] are capable of generating the 7L voltage as well as voltage boost capability of 1.5, but these topologies require a higher number of switching devices with higher values of total standing voltage (TSV). The topologies in [12,13] can generate a nine-level output, but these topologies lack the boosting feature. Table 3 is evident that the proposed 7L topology gives a better design in terms of all aspects as compared to other topologies. For analysing the efficiency comparison, in this work, the switched capacitor MLI topologies are considered which are having similar features such as 7L voltage with a gain of 1.5, as illustrated in Fig. 6. The proposed 7L topology has higher efficiency as compared to all other topologies due to the lower number of components used, i.e. switches as well as capacitors which result in reduced losses. In addition, as only one capacitor is used for each half-cycle a fundamental period will result in the reduction of ripple losses associated with the capacitors. From Fig. 6, it is observed that the proposed topology gives higher efficiency for different ratings of the output power as compared to the topologies in [6,7,9,11].

Results and discussion
The proposed 7L-SCBI is validated experimentally by using the laboratory prototype, as shown in Fig. 7. The parameters used for validating the experimental prototype are described in Table 4. The control logic pulses for proposed 7L-SCBI are generated with the help of Field Programmable Gate Array (FPGA) Vertix-5, XC5VLX50T controller. For avoiding the short-circuit possibilities of the DC source, 2 µs delay is provided between the complementary switches S 7 and S 8 , S 5 and S 6 . The experimental result of the proposed 7L-SCBI with the resistive + inductive load (RL-Load, 150 Ω and 80 mH) is illustrated in Fig. 8a. The output voltage peak magnitude is 300 V for a given input voltage of 200 V, i.e. the boost factor is 1.5 as shown in Fig. 8a. The capacitors C 1 and C 2 are charged to 100 V equally, which is half of the input DC-link voltage. The experimental results of the proposed 7L-SCBI under the step change in the R-Load, i.e. two R-Loads (two 150 Ω loads) connected in parallel are given in Fig. 8b. The peak of the load current changes from 2 to 4 A which can be clearly observed from Fig. 8b. In this figure, zoomed version of the output voltage and currents is also presented.
The experimental results of the proposed inverter with the change in power factor (changing the load from R-Load to RL-Load) are shown in Fig. 9a. From this figure, it can be seen that with the R-Load the power factor is unity, after switching the load to RL-Load the power factor is reduced to 0.986 lagging [cos(X L / R)]. The experimental results during the starting time of the proposed 7L-SCBI prototype are presented in Fig. 9b. This figure is evident that the capacitors are charged slowly from 0 to 100 V in the first few cycles. During this time, the transients in output current and voltage of the inverter are minimal. It also shows that the proposed topology does not require any pre-charging circuit for the capacitors, and they are self-balanced without any auxiliary circuit.

Conclusion
A 7L-SCBI configuration is presented in this paper with the significant advantages that are essential for PV and fuel cell applications, such as voltage boosting capability, multilevel output voltage with the minimum order of switching device and passive components, and higher efficiency. At the output side, for achieving the voltage boost factor of 1.5 from the given input DC voltage the proposed inverter requires only two capacitors and eight power switches (voltage blocking rating is ≤V dc ). The experimental results are evidence for better performance under various operating conditions.

Acknowledgments
This publication was made possible by Qatar University-Marubeni Concept to Prototype Development Research grant # [M-CTP-CENG-2020-2] from the Qatar University. The statements made herein are solely the responsibility of the authors.