Sensorless DTSMC of a three‐level VSI fed PMSM drive

This study proposes a novel sliding mode control (SMC) structure for a three-level voltage source inverter (VSI). The proposed controller is implemented in discrete time and is applied for the closed-loop speed control of permanent magnet synchronous motor (PMSM) drive powered from a three-level cascaded H-bridge VSI. The proposed discrete time SMC (DTSMC) has the distinct advantages of control over maximum switching frequency and relatively lower total harmonic distortion compared to that of a conventional hysteresis modulation (HM) control. Unlike HM, the proposed DTSMC relates the maximum switching frequency to sampling time, resulting in better utilisation of the bandwidth of the VSI. Additionally, a procedure to combine the DTSMC with a sliding mode observer to achieve sensor-less operation of the PMSM drive is presented. Verification of the proposed DTSMC is conducted using simulation and experimental tests. The simulation and experimental results are presented.


Introduction
Permanent magnet synchronous motors (PMSMs) are known for their high efficiency, compact size and high torque density [1]. They are used in various applications such as machine tools, robots, missiles, air crafts, satellites, wind energy generators and electric vehicles [1][2][3][4], where low weight and compact size are important. Generally, PMSM drives are powered from voltage source inverters (VSIs). The control of these VSIs requires that the continuous control signals be given as a digital ON/OFF pulse train to trigger the switches of the converter. The algorithms that convert the continuous control signals into digital pulse trains can be classified into two broad categories, namely carrier-based pulse width modulation (PWM) [3,5,6] and hysteresis modulation (HM) [7][8][9][10]. In carrier-based PWM strategies, an analogue voltage reference is compared with a high-frequency carrier signal to generate an output pulse train with a constant switching frequency [3,5,6]. In HM, the actual current is directly compared with a current reference signal and the error is passed through a hysteric relay which yields the switching state S state of the converter [7][8][9][10]. The output voltage of the converter V o is a function of the DC-link voltage V dc and the switching state S state as follows: The advantage of control algorithms based on carrier-based PWM is the fixed switching frequency of the inverter, however its performance is sensitive to system parameters. HM is known for its robustness to load parameter variations, fast dynamic response and inherent overcurrent protection. However, HM suffers from the disadvantage that the switching frequency varies over a wide range and there is no mathematical relation to determine, hence to control, the maximum switching frequency [11]. The hysteresis band will be selected manually using trial and error method. This not only results in high torque and current ripple with varying ripple frequency but also makes it difficult to determine the switching losses. Also in certain applications, the design of output filter becomes a challenging task [7]. Several methods to achieve fixed frequency in two-level HM are suggested in the literature [12,13]. The multi-band approach [12], multi-offset approach [14] and variable HM band [9] generally require additional feedback signals to adjust the hysteresis bands and introduce dc tracking errors. The space vector based HM strategies [15,13] use space vectors stored in the form of a look-up table to select the best voltage vector but suffers from the limitations such as lack of control over the maximum value of the switching frequency and switching frequency variations. These techniques do not limit the maximum switching frequency to a predetermined value, however, they help in narrowing down the switching frequency variation range.
The problem of controlling the maximum switching frequency can be addressed using sliding mode control (SMC) implemented in discrete time (DT) [11]. Like HM, SMC is also a non-linear robust control approach which changes the system structure to make the system state variables move along the desired sliding mode trajectory. The ideal SMC theoretically resembles the HM with zero hysteresis band and lead to infinite switching frequency [2,16]. Under these conditions, the response is excellent. However, owing to the limited controller frequency, bandwidth and the inertia of the electrical systems, the sliding mode function switches with high yet finite frequency resulting in chattering. The chattering of sliding mode controllers in power converters is reflected on the THD.
Field oriented control (FOC) [6,17] and direct torque control (DTC) [18][19][20][21] are the two widely used closed-loop speed and torque control algorithms for PMSM drive. Conventional approach for FOC consists of properly tuned cascade control structure of proportional-integral (PI) speed and torque controllers, implemented using carrier-based PWM strategy [22]. This requires accurate information of motor parameters and load conditions in order to guarantee stability and good drive performance in terms of accuracy, disturbance rejection and bandwidth [17]. The FOC can be made robust by replacing these PI controllers by SMC. However, as stated in [17,23], the VSC cannot be applied for the outer speed control loop as the reference input to the inner current loop must have bounded time derivatives. In this paper, the threelevel SMC is applied only to the inner current controllers. The outer speed loop is realised using PI controller but the feedback speed signal is estimated by designing proper sliding mode observer (SMO) [24].
Conventionally two-level inverters are used in PMSM drives [3,4,17,24]. Recently, the multilevel inverters are preferred over conventional two-level inverters due to several advantages like ability to synthesise near sinusoidal output voltage waveforms with low voltage rating switching devices, low dv/dt, improved total harmonic distortion (THD) and increased reliability. Among the multilevel topology, the cascaded H-bridge (CHB) inverter has modular structure and simple power circuit, resulting in higher reliability, thus preferred in variable frequency drives [25][26][27]. Hence, a three-level CHB VSI fed PMSM drive is used in this paper.
The objective of this paper is to address the two major problems associated with the conventional HM for a three-level VSI fed PMSM drive, namely, (i) large variation in switching frequency and (ii) lack of control over the maximum switching frequency. In the proposed DTSMC, the maximum switching frequency is a function of sampling frequency, resulting in full control over the maximum switching frequency. This allows setting the maximum switching frequency such that it satisfies the limits of the power semiconductor devices. In conventional HM, a trial and error process is utilised to set the maximum switching frequency. This results in the drawback of using a low average switching frequency and thus under-utilisation of the hardware bandwidth. Limiting the maximum switching frequency while using HM is challenging in multilevel VSIs. An n-level inverter normally has (n − 1) hysteresis bands and hence adjusting many variable bands becomes complicated [9]. The proposed DTSMC however does not suffer from this drawback as the maximum switching frequency in multilevel VSIs can be easily set. Another advantage of the proposed DTSMC is it reduces the variation of switching frequency compared to that of conventional HM, resulting in better utilisation of the bandwidth of the hardware. The narrow range of switching frequency variation means reduced current ripple, reduced torque ripple and better THD. With the proposed threelevel DTSMC, not only full control over the maximum switching frequency is achieved but also additional advantages such as use of lower voltage rating device, output voltages with low dv/dt and further reduction in THD can be achieved due to three-level operation.
Another novelty of this paper is a new method of updating the switching states in a digital controller. In this method, by using the reachability condition associated with the analysis of sliding mode controllers. The internal states are considered and switching states are updated using updated internal states. This results in lower THD. The advantage of the proposed DTSMC is that it can be an alternative to carrier-based regular sampled PWM method with faster and more robust control dynamics.
The paper is organised as follows. The SMC, its limitation on DTSMC and the DTSMC are explained in Section 2. The performance of the proposed control structure, in terms of THD and switching frequency variation is compared against that of the HM for a three-level inverter and these results are given in Section 3. The proposed DTSMC is verified through simulation and experiment by applying to the closed-loop speed control of PMSM powered from a three-level CHB inverter. The simulation and experimental results are given in Section 4. Finally, Section 5 concludes the paper.

Three-level DTSMC
The power circuit diagram of the three-level CHB inverter is shown in Fig. 1. It has one H-bridge in each phase and is capable of generating phase voltages with three levels namely 0, +V dc and −V dc . The inclusion of the third level allows for a zero-voltage output state meaning that S state = 0 is defined. For three-level inverters, three-level HM can be applied by defining S state via the current error e i = i * − i using the switching function, with a hysteresis band (b) shown in Fig. 2 which can be implemented through adding the outputs of two hysteresis relays [7][8][9]. The discontinuous switching nature of HM for a two-level inverter resembles the structure of sliding mode controllers. In its standard form, SMC is defined as k sgn(σ) where σ represents the sliding variable to be driven to zero under ideal sliding mode operation [28,29]. The proper operation of the controller is guaranteed by satisfying the reachability condition which is an extension of Lyapunov's stability theory given by where σ is the time derivative of σ and η is a positive constant that is inversely proportional to the convergence time.
To achieve ideal sliding mode, the system must be characterised by an input relative degree of one, meaning that the control appears in the first derivative of the sliding variable such that it can be expressed as where χ is a bounded function of the system states and disturbances, and u smc represents the output of the SMC. It is critical to note that for two-level HM, the sliding variable is defined as the phase current error σ = i * − i and the control u smc which yields the switching state can be represented in the standard form S state = sgn(σ).

Introduction of zero-state voltage
The standard form of SMC can be directly applied to two-level inverters. However, it has to be modified when applying SMC to the control of three-level inverters in order to include the zero state S state = 0. Hence, this paper proposes a modified structure which, unlike HM, takes into account the reachability condition. The following control law is considered such that: Substituting (3) and (4) into (2) yields For sgn(σ) = sgn( χ), (5) can be expressed as which is satisfied for a sufficiently large value of k and governs the convergence time as η ≥ k − χ. For sgn(σ) ≠ sgn( χ), then (5) can be expressed as Here, χ, which appears due to the natural response of the system, determines the convergence time. Fig. 3 shows the proposed three-level DTSMC which defines S state of a phase of the three-level inverter. The resultant control becomes u smc = V dc S state and can be expressed as (5) with k = V dc and χ determined by the characteristics of the connected load. Under ideal sliding mode operation, the switching frequency is infinite. In practical applications, if the maximum switching frequency is not limited, the switching will occur at very high but finite frequency which will lead to high switching losses, missing switching pulses due to narrow pulses and sometimes failure of the switching devices. It is essential to limit the switching frequency to a safe practical upper limit which is decided by the switching capabilities of power semiconductor switches. Currently, the power semiconductor switches with switching frequency of the order of few hundreds kHz are available for medium power ranges, thanks to the advancement in the semiconductor technology. But even with this high finite switching, the ideal characteristics of SMC will be affected [2,11,16]. In digital controllers, the maximum switching frequency can be limited by implementing the SMC in DT where the switching states are updated in every sampling period. If allowable maximum switching frequency is f max , the sampling period is chosen to be twice f max . Conventionally, this is achieved by including a small hysteresis band (b) as done in HM [11,30]. However, the limitation of this approach is that, there is no mathematical relation that relates b to the maximum switching frequency and b will be determined manually by trial and error. This paper proposes a better approach, where a zero-order hold (ZOH), with one sample period is used with the SMC as shown in Fig. 3.

DTSMC for a three-phase system
A three-level inverter powering a Y-connected active inductive load with back emfs e a , e b and e c as in Fig. 1 is considered for DTSMC implementation. The i a , i b and i c are the currents in phases A, B and C, respectively. In this three-phase system, the phase voltage is a function of the switching states S a , S b and S c as per (8). This essentially means that for one phase, the impact of the other two phases can be regarded as part of By defining the sliding variable σ a for phase A as the current error, the following expressions can be generated: where Similarly, the sliding variables σ b and σ c (the current errors for phases B and C, respectively), can be defined as where χ b and χ c are given by Following (4) and Fig. 3, the switching states are defined as It should be noted that the proposed structure takes into consideration not only the current error but also its derivative based on the reachability condition while designing sliding mode controllers. In the conventional approach of switching, the switching states of all three phases are updated simultaneously once in every sampling period T s . In this paper, as illustrated in Fig. 4, χ a and S a for phase A are calculated based on pre-existing values of S b and S c . The switching states of phase A are updated at T s /3, instead of T s . The χ b and S b for phase B are calculated by using new value of S a and the pre-existing value of S c . The switching states of phase B are updated at 2T s /3. Similarly, the switching states for phase C are calculated using the new values of S a , S b and updated at T s . Unlike the conventional method, update of the switching states is not done simultaneously every T s ; rather, new data is acquired and updates are made every T s /3 one phase at a time. While each phase switches only once every T s , the overall output voltage is updated every T s /3 using new data. This results in reduced current ripple which in turn results in reduced harmonics. This is verified in the next section through simulation results.

Three-level DTSMC with passive RL load
The developed current control strategy is first tested on the system shown in Fig. 1 with a passive inductive load of L = 10 mH and R = 30 Ω. For a passive load, e a = e b = e c = 0 V. The upper limit for the maximum switching frequency is set at ( f max = 5.55 kHz).
To accomplish this, a sampling period of T s = 90 μs is selected for DTSMC implementation. A balanced three-phase current reference of peak amplitude i * = 4 A and fundamental frequency f 1 = 50 Hz is selected. The results using the proposed three-level DTSMC is compared with that of the three-level HM and carrier-based PWM algorithms. In order to do fair comparison, in HM, the hysteresis The b = 1.17 A is found to limit the f max to 5.55 kHz for the given system. For carrier-based PWM, the carrier frequency is set equal to f max = 5.55 kHz and modulation index is set to impress required voltage to obtain i = 4 A for the above load. The line-line voltage (v ab ) is shown in Fig. 5. As can be seen in Fig. 5, the zero state voltage is successfully produced by the DTSMC and five levels are produced. Fig. 6 presents the switching frequency variations for the proposed DTSMC and for HM. In the proposed method, the ZOH operation sets a maximum frequency limit of f max = 5.55 kHz and on average operates at a higher frequency compared to HM. As seen in Fig. 6, even with precise adjustment of b, the HM switching frequency is far below the maximum switching frequency and rarely touches the maximum switching frequency limit. Due to this, the proposed DTSMC results in lower current ripple and better THD compared to HM as shown in the plot of phase A current (i a ) in Fig. 7 and its harmonic spectrum in Fig. 8. Note that the y-axis of Fig. 8 is magnified for better clarity of harmonic components and the peak values of the fundamental components of i a are 3.98 A for DTSMC, 3.92 A for HM and 3.99 A for carrier-based PWM, respectively. The DTSMC results in lower current THD of 12.32% compared to 15.5% of HM as illustrated in Fig. 8. The carrier-based PWM operates with a fixed switching frequency of 5.5 kHz, so the current ripple is low as in Fig. 7c and has a better THD as shown in Fig. 8c. In carrierbased PWM, the switching frequency is decided by the carrier frequency and it is designed based on the maximum switching  capacity of the semiconductor switches. It is worth noting that the carrier-based PWM technique uses inner current controller made up of PI controller and this decides the voltage to be impressed on the system to get desired current. The performance depends on the system parameters and tuning of the PI controller. So, the carrierbased PWM technique has better switching characteristic and output THD but poor dynamic response compared to HM. Fig. 9 shows the plot of current error of phase A. The results show that compared to HM, the proposed DTSMC has lower current error, resulting in higher average switching frequency as in Fig. 6 and reduced current ripple as evident in Fig. 7. It can be observed that in HM, the f max cannot be estimated whereas the proposed DTSMC f max can be determined and the inverter switches near the predetermined f max .

Three-level DTSMC for speed control of PMSM
The proposed DTSMC is applied to the FOC of PMSM drive [24] powered from a three-level VSI. DTSMC in the inner current loop with FOC control for speed control retains the features of both conventional FOC and DTC methods [11]. The functional block diagram of the DTSMC is shown in Fig. 10. The FOC is well published in the literature [6], so only minimum details are given in this paper. In order to retain the decoupling features of the FOC, the DTSMC is implemented in rotating d-q reference frame. The FOC of PMSM consists of cascaded control structure. The output of the outer speed controller provides the reference input to the qaxis current controller. The reference input (i q * ) is proportional to the motor torque, so the q-axis current controller provides the torque control. The d-axis component of the current determines the motor flux and for constant flux operation the d-axis reference (i d * ) = 0.
In order to achieve complete decoupling, rotor flux axis is taken as the reference axis in FOC. By referring to the rotor flux axis reference, the dynamics of a three-phase PMSM can be expressed as [6,11] di ds dt = 1 L s V ds − R s i ds + ω e L s i qs (19) di where i ds , i qs are dq components of the stator current (A); V ds , V qs are components of the stator voltage (V); Ψ r is permanent magnet flux linkage (Wb); R s is stator resistance (Ω); L s is stator inductance (H); P is number of poles per phase; T m , T load are output torque of motor and load torque (Nm); J is rotational moment of inertia (kg ⋅ m 2 ); B m is drag coefficient (Nm ⋅ s/rad); ω m , ω e are mechanical and electrical rotor speed (rad/s) As per (21) and (22), the FOC can be used to directly control the output torque T m , hence speed, by controlling i qs . The Park's transformation (24) to compute d -q components from the fixed reference frame axis α − β components, requires the knowledge of the rotor angle θ r . In this paper, θ r is estimated using a SMO which is explained in the next subsection

Sliding mode observer
To obtain a proper estimate of θ r and eliminate the need for speed and flux or position sensors, a SMO is used [16,[31][32][33]. The electrical model of the PMSM given by (19) and (20) in the rotor frame is transformed to the fixed reference frame as di βs dt = 1 L s V βs − R s i βs − ω e ψ αr (27) dψ αr dt = − ω e Ψ r sin(θ r ) = − ω e ψ βr (28) dψ βr dt = ω e Ψ r cos(θ r ) = ω e ψ αr , where ψ αr and ψ βr represent the αβ-components of Ψ r translated to the stationary reference frame. To attain proper estimates of ω m and θ r , the following SMO, given in the stationary reference frame, is used: where the hat notation on a variable (x) indicates the estimated value of the actual variable and k ψ is a positive constant. Analysis of the sliding action of the observer can be done by defining the sliding variables as The sliding action for this observer is introduced through the discontinuous corrections signals μ α and μ β given by The notation (x¯) symbolises the estimation error (x − x^). For a sufficiently large value of k c , the reachability condition in (2) is satisfied. This guarantees that SM operation is achieved and the current errors converge in finite time. For (30)-(33), the speed estimate is obtained through ω e = μ α + ω e ψ βr eq 2 + ω e ψ αr − μ β eq where the subscript 'eq' represents the average or equivalent value of the variable, obtained by passing the variable through a low-pass filter of relatively low time constant. These values should satisfy ((dσ α /dt) = (dσ β /dt) = 0). Accordingly, to prove proper speed estimation, the equivalent values are obtained by subtracting (30) and (31) from (26) and (27) di¯α s dt = 0 = ω e ψ βr − ω e ψ βr − μ α eq (39) di¯β s dt = 0 = ω e ψ αr − ω e ψ αr − μ β eq Hence μ α eq = ω e ψ βr − ω e ψ βr (41) μ β eq = ω e ψ αr − ω e ψ αr (42) Substituting (41) and (42) into (38) yields ω e = ω e proving the credibility of speed estimation for ω e > 0. To reduce chatter in the estimation, the discontinuous sgn σ can be replaced by a continuous boundary layer approximation as a saturation function sat(σ/ε) where ε is a small positive number. To show the convergence of the flux errors ψ αr and ψ βr , (41) and (42) can be substituted into (32) and (33) to yield dψ αr dt = − k ψ ω e ψ αr (43) which confirms the convergence of the errors. The unit vectors cos(θ r ) and sin(θ r ) required for the Park transformation of computing d -q components from a -b -c and vice versa can be estimated from the estimated value of flux components as in the following equations: For the calculations of χ a , χ b and χ c in (11)

Simulation results of DTSMC of PMSM
The control structure shown in Fig. 10 is first verified through simulation using Matlab/Simulink. The parameters for the PMSM used in the simulation are obtained from an actual test motor and are given in Table 1. The same parameters are used for experimental verification also. The parameters for the SMO were set to k ψ = 40 and k c = 30 and the load torque T load is kept constant at 7.5 Nm. The results of the simulation are given in Fig. 11. Fig. 11a presents the plot of measured rotor flux components and the flux components estimated using SMO. The SMO is tested for different initial conditions. As shown in Fig. 11a, the SMO achieves proper estimation of ψ αr and ψ βr and leads to the convergence of the estimation errors under different initial conditions. In Fig. 11a, the estimated value of flux components converge within 0.05 s. This leads to the satisfactory control of the speed as shown in Fig. 11b for a reference speed of N m * = 750 rpm. Figs. 11c and d give the plot of motor stator currents (i a , i b and i c ) and motor line voltage (v ab ), respectively, under above test conditions for the proposed DTSMC. With a maximum switching frequency of ( f max = 5.55 kHz), the motor current exhibits a THD of 7.2%. In order to make a fair comparison, HM with a hysteresis band adjusted to get a maximum switching frequency of 5.55 kHz is used. It should be noted that the value of b = 0.61 is obtained by trial and error, to limit the maximum switching frequency to 5.55 kHz. Under these conditions, the motor current has a THD of 9.5% for HM.

Experimental verification of DTSMC of PMSM
The experimental prototype of the system shown in Fig. 10 is fabricated in the laboratory. The experimental results are given in Figs. 12 and 13. The picture of the experimental setup is shown in Fig. 14 Step down transformers (400 V/150 V) are used to match the input voltage to get desired V dc and also to provide galvanic isolation. A separately excited DC machine is coupled with the PMSM motor and is used as generator to load the PMSM motor. A tacho generator with a gain of 1 V/1000 rpm is used to measure the actual shaft speed. The parameters of the experimental hardware setup and the motor ratings are same as that used in simulation as in Table 1.
In the experimental setup, the two line currents (i a and i b ) are measured using Hall sensors and i c is calculated as i c = − (i a + i b ). The DC-link voltage V dc is also measured. The phase voltages (v a , v b and v c ) are computed from the V dc and switching states S a , S b and S c using (8). From phase voltages, the stator voltage components V αs and V βs are computed using a -b -c to α − β transformation. The SMO, given by (30)-(38) is then implemented on the dSPACE. From the SMO, the unit vectors cos(θ r ) and sin(θ r ) are computed using (45) and (46), respectively. These unit vectors are  used for axis transformation and to obtain i ds and i qs as per (24). The speed estimate ω e is also taken from the SMO using (38) and used in the external loop of the FOC for speed control. The external speed loop uses PI controller, which generates the current reference signal i qs * which is then transformed to the abc-axis. The back emf e a , e b and e c are estimated using (47) and are used for DTSMC implementation by calculating first χ a , χ b and χ c via (11)- (15). The switching states S a , S b and S c are computed using (16)- (18). This completes the DTSMC closed-loop sensorless topology.
The steady-state flux response follows a sinusoidal pattern at the reference electric frequency of 25 Hz (corresponding to N m = 750 rpm) which suggests proper estimation of ψ αr and ψ βr as shown in Fig. 12a. These results match with the simulation results shown in Fig. 11a. The speed control is achieved as seen in Fig. 12b and it also shows that the estimated speed (N m ) matches the actual measured speed (N m ). For a load torque of (T load = 7.5 Nm), the steady-state motor currents of two phases (i a and i b ) and the line-line voltage v ab are shown in Figs. 12c and d, respectively. The experimental results match with the simulation results. The motor current has a THD of 8.6%. Fig. 13 shows the torque and speed response for a step increase in load torque from 17 to 100% of full load torque. The SMO retained proper function and speed control is satisfactory. This verifies the ability of both the SMO and the DTSMC to track the currents.

Conclusion
In applications that require fast and robust control, the HM is more preferable than the carrier-based PWM. While HM provides good control performance, it suffers from the limitations such as difficulty in predicting maximum switching frequency for a given hysteresis band, low average switching frequency and wide variation of switching frequency. The proposed three-level DTSMC is a better alternative to HM. Through DTSMC, the maximum switching frequency can be set to desired value and it is a function of sampling time. In addition, by considering the reachability condition and adopting a new method of updating the switching states, the proposed three-level DTSMC is able to ensure robust tracking of the current references, resulting in lower harmonics compared to the HM for a given maximum switching frequency limit. In this paper, the proposed three-level DTSMC structure is applied for the speed control of PMSM. The performance of the proposed three-level DTSMC is verified through simulation and experiment, both of which give satisfactory results. The proposed method will find application in areas such as electric vehicles and high performance drives for machine tool applications, where fast control dynamics of speed or torque are needed and the hardware switching limitation must be enforced. Extending the proposed controller to other multilevel converter applications is an interesting work for the future.