Flexible memristor-based LUC and its network integration for Boolean logic implementation

Memristor is a nanoscale electronic element with variable resistance that depends on the amount and direction of the charge passing through it. As a promising candidate, this memristive element opens up a new approach for the implementation of Boolean logic operations. In this study, a flexible logic unit circuit (LUC) based on a practical memristor model is proposed, which is able to perform the AND, OR, NOT, NOR, and NAND gate operations by different switch settings. Unlike existing memristor-based logic implementation, the initialisation is not necessary for the proposed method, and the total delay can be effectively reduced, especially for time-sequence inputs. Furthermore, the concept of the memristor-based logic network is developed by multiple memristor-based LUCs connected in series and parallel. The circuit simulation demonstrates that the presented logic network is capable of realising multi-input–multi-output logic operations with compact structure, high efficiency, and sufficient accuracy.


Introduction
As the traditional CMOS technology gradually scales down to the inherent physical device limits, it has been facing a series of challenges associated with the increased leakage power consumption, reduced stability, and so forth [1].To effectively address these challenges, several remedies have been proposed [2][3][4].Among them, the recent advent of memristors has become one of the powerful candidates for addressing the design issues related to the continued scaling.The memristor was theoretically postulated by Chua [5] but had not been physically realised until 2008 by the Hewlett Packard (HP) laboratory [6,7].As the fourth fundamental circuit element [7], memristor possesses many advantageous properties such as nanoscale geometry, variable conductivity, non-volatility, low power etc. [8][9][10][11][12][13][14][15].Particularly, memristor provides an unconventional computation framework which combines information processing and storage in the memory itself [16].This justifies the considerable attention gained by unconventional memristor-based computing and logic circuits [17].So far, there has been some work related to the memristor-based logic implementation [18][19][20][21][22][23][24][25][26][27][28][29].Normally, the previous work can be roughly classified into four sorts as below: i. Material implication-based logic: The specific computation of logic functions is realised by imply and reset logic operations [18,19].The circuit implementation is simple and the response of logic operation is fast.ii.Hybrid memristor/CMOS-based logic: All the logic operations are performed by the integration of memristors and CMOS components [3,[20][21][22][23], which indicates that the memristor can be fabricated with the CMOS metal layers, and the physical integration area can be significantly saved.iii.Crossbar-based (CB) logic: The logic operations are realised in memristor crossbars by leveraging the programmability of the memristor at cross-point [24][25][26].The crossbar structure could promise the benefits of fabrication simplicity, pattern regularity, and defect tolerance.iv.Memristor-only logic: The logic circuit only consists of memristive elements, and the output state variable is stored as the memristance directly [27][28][29].Generally, these circuits are able to perform the basic logic operations with simple seriesparallel configurations.
Although the above-mentioned approaches are able to perform the basic logic operations, they all inevitably suffer from some limitations such as the operational complexity and physical realisation.Specifically, memristor-based imply logic always requires lengthy sequences of stateful logic operations for synthesising a given Boolean logic function [19].In the majority of memristor/CMOS logic, the main issue is that the compatibility between the memristive elements and CMOS units is not as good as expected due to the natural differences between the nanoscale devices and conventional transistors [23].One of the main challenges in CB logic is the sneak paths problem [24].In memristor-only logic, initialisation is necessary for each logic operation, which greatly increases the total delay, especially for time-sequence inputs [27].In addition, a common defect in existing memristor-based logic implementation is the lack of a general logic unit circuit (LUC) for implementing all basic logic operations effectively.Thus, this paper further investigates the memristor-based logic circuit design approaches.The main contributions are summarised as follows: i.A flexible memristor-based LUC (M-LUC) is presented, which is able to realise the basic AND, OR, NOT, NOR, and NAND gates by different switch settings.ii.Unlike the majority of other memristor-based logic implementation, initialisation is no longer necessary in the proposed method, which significantly reduces the total delay and makes the entire process more efficient.iii.A compact logic network is developed by multiple M-LUCs connected in series-parallel configurations, which enables the implementation of complex multiple-input-multiple-output (MIMO) logic functions.operations.On the basis of the multiple M-LUCs connected in series-parallel configurations, a compact memristive logic network is designed in Section 4. Section 5 provides a robustness analysis (mainly considering the process variations) for the proposed logic circuit.In Section 6, a series of circuit simulations are carried out to demonstrate the validity and effectiveness of the entire scheme.Finally, Section 7 concludes the entire work.

Memristor basics
The memristor is essentially a non-linear passive electronic device with memory capacity.As one of the most widely used memristor models, the HP model is a promising candidate in memristor-based logic implementation [18].Specifically, it is made up of a doublelayer thin film of titanium dioxide (TiO 2 ) (thickness: D) sandwiched between a pair of platinum electrodes [30,31].Owing to the different conductive ability, the two TiO 2 layers are defined as doped and undoped regions.Generally, an external stimulus applied across the memristor may cause the charged dopants to drift and the doping front between these two regions would be moved correspondingly with changes of the total memristance.Then, the overall resistance of the HP memristor (i.e. the memristance) can be mathematically expressed by [30,31] where R L and R H denote the lowest and highest resistances, respectively; w(t) is the time-dependent length of the doped region; x(t) is the internal state variable within the range of [0, 1], and its dynamic function is given by where parameter η = ±1 denotes the polarity of the memristor and µ v is the average ion mobility with the value of 10 −14 m 2 s −1 V −1 approximately; i(t) is the current flowing through the memristor; and f p (x) = 4x − 4x 2 is the window function that models inevitable non-linear ion drift phenomenon near the boundaries of nanoscale devices [30].
From ( 1) and ( 2), the change rate of memristance can be obtained by where a = 4kη/ΔR (ΔR = R H −R L ), b = R L + R H , and c = R L R H are all constants, V(t) is the voltage applied to the memristor.
Integrating both sides of (3) where R 0 is the initial memristance and R Obj is the corresponding objective memristance.Assuming φ 0 = 0, the total magnetic flux required for the memristance variation from R 0 to R Obj can be calculated by where parameter ɛ is a constant close to zero.It is used to make sure that ( 5) is valid in any case.On the basis of [9], when the value of ɛ is sufficiently small (ɛ≤10 −2 ), it has a negligible impact on the calculation of the flux required for memristance variation.For convenience, parameter ɛ is uniformly set as ɛ = 10 −3 for all the computer simulations in this paper.
On the basis of (5), if the external stimulus is a fixed voltage V, the switching time for memristance variation can be calculated by From Fig. 1, when a positive voltage is applied to the memristor, the current flows through the nanoscale device from its positive polarity to the negative polarity (labelled by a thick black line), so that the memristance will rapidly decrease to its lowest value R L (denoted by the blue-solid line).On the contrary, when a negative voltage is applied to the memristor, the direction of current is opposite, and the memristance will increase to its highest value R H within a short time (denoted by the red-solid line).In particular, the switching time for memristance variation ΔT 1 (ΔT 2 ) can be calculated by (6), which is useful to estimate the total time of the presented memristor-based logic implementation.

Proposed M-LUC
In this section, a flexible M-LUC is proposed.It is able to realise the basic Boolean logic gates (including AND, OR, NOT, NAND, and NOR gates) through different switch settings.The process description is given as follows.

Design of the M-LUC
The M-LUC mainly consists of two regions, i.e. the regulatory region (labelled by the green dashed box) and the load region (labelled by the blue dashed box), as shown in Fig. 2. From Fig. 2, M 1 , M 2 , M 3 , and M 4 connected in the regulatory region are four identical memristors, whose limiting memristances are denoted by R L and R H , i.e.R j ∈[R L , R H ], (j = 1, 2, 3, 4).Meanwhile, the remaining two memristors (M s1 and M s2 ) named as the load memristors in the load region are also the same, whose resistances vary from R SL to R SH , i.e.R sj ∈[R SL , R SH ], (j = 1, 2).To successfully realise different logic operations, the memristance relationship should always satisfy R s1, s2 ≫R 1, 2, 3, 4 .V 1 and V 2 are the two time-sequence inputs of the M-LUC.The output of the M-LUC is denoted by the load memristance R sj , (j = 1, 2).Notably, considering the impact of the process variations on the memristor [32,33], a threshold resistance M thre ∈(R SL , R SH ) is added to define the relationship between the outputs and the logic states, namely Then, the realisation procedure of different Boolean logic gates is elaborately described as below.

Implementation of basic Boolean logic gate operations
In this section, five basic Boolean logic gate operations are introduced using the presented M-LUC.

AND gate:
On the basis of the proposed M-LUC, the switch setting for the implementation of AND gate is provided first.Specifically, the switches connected to the memristors M 1 , M 2 , and M s2 should be turned into A 1 , B 1 , and C, respectively.The remaining switches are all connected to the floating terminals, and the relevant memristors M 3 , M 4 , and M s1 are in the idle state.
According to Kirchhoff's current law, we have where constant voltage V c denotes the voltage of the node C.
Since R s2 ≫R 1 , R 2 , the value 1/R s2 can be omitted.The voltage at the common node V s can be approximately calculated by where voltages V 1 and V 2 denote the input logic state variables.Specifically, the high-level voltage V H = 5 V designates the logic '1', while the low-level voltage V L = 0 V designates the logic '0'.The constant voltage V c is set to V c = 0.5 and V H = 2.5 V. On the basis of the various states of the input signals V 1 and V 2 , three possible cases can be summarised as below: , the node voltage V s is equal to V H approximately.According to the memristance variation rule (as illustrated in Section 2), the current flows through the load memristor (M s2 ) from its positive polarity to the negative polarity, and the load memristance R s2 will rapidly reduce to its lowest value R SL .Since R SL <M thre , the load memristance represents the logic '1'.

Case b:
Contrary to Case a, the current flows through the nanoscale device (M s2 ) from its negative polarity to the positive polarity, and the load memristance R s2 will sharply increase to its highest value R SH (R SH >M thre ), which represents the logic '0'.Case c: , the node voltage V s can be expressed by On the basis of the memristance variation rule, the resulting node voltage V s in (10) can be calculated by Similar to Case b, the current flows through the load memristor from its negative polarity to the positive polarity, and the load memristance R s2 will increase to the highest value R SH (R SH >M thre ), which represents the logic '0'.

OR gate:
Different from the AND gate, the switch setting for OR gate is given as follows: the switches associated with the memristors M 3 , M 4 , and M s2 are adjusted to A 1 , B 1 , and C, respectively, while the switches connected with the memristors M 1 , M 2 , and M s1 are all tuned into the floating terminals.
According to Kirchhoff's current law, the node voltage V s can be approximately calculated by On the basis of the states of two input signals V 1 and V 2 , three possible cases can be collected as follows: Case a: (11), the node voltage V s ≃V H .The current flows through the load memristor from its negative polarity to the positive polarity, and the load memristance R s2 will reduce to its lowest value R SL (R SL <M thre ) in a short time, which represents the logic '1'.

Case b:
The current flows through M s2 from its negative polarity to the positive polarity, and the load memristance R s2 will increase to the highest value R SH (R SH >M thre ), which represents the logic '0'.

Case c:
, the voltage at the common node V s can be computed by On the basis of the memristance variation rule (as illustrated in Section 2), the node voltage V s in (12) can be computed as V s ≃R H V H /(R L + R H )≃V H .The current flows through the load memristor from its positive polarity to the negative polarity, and the load memristance R s2 will reduce to its lowest value R SL (R SL <M thre ), which denotes the logic '1'.

NOT gate:
As for NOT gate, the switches connected with the memristors M 3 and M s1 are turned into A 1 and C′, respectively, while the rest of the switches (referring to the memristors M 1 , M 2 , M 4 , and M s2 ) are all put into the floating terminals.Then, the node voltage V s can be computed by Since R s1 ≫R 3 , (13) can be directly simplified as On the basis of the state of the input signal V 1 , two possible cases can be summarised as follows: Case a: When V 1 = V H , the voltage applied to the load memristor M s1 is V s −V c ≃2.5 V.The current flows through M s1 from its negative polarity to the positive polarity, and the load memristance R s1 will increase to its highest value R SH (R SH >M thre ) which represents the logic '0'.

Case b:
The current flows through M s1 from its positive polarity to the negative polarity, and the load memristance This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)R s1 will decrease to the lowest value R SL (R SL <M thre ), which represents the logic '1'.
In addition, the presented M-LUC can also be utilised to perform the NAND and NOR gate operations.Since the principle of NAND (NOR) operation is almost the same as the aforementioned AND (OR) operation, except for changing the polarities of the memristors in the load region, the relevant process description will not be repeatedly provided.For clarity and simplicity, the overall information of the aforementioned five logic gates is collected in Table 1.
From Table 1, the obtained input-output (IO) relationships indicate that the presented M-LUC is able to perform the five basic Boolean logic gate operations through the corresponding switch settings.On the basis of this, some complex Boolean functions can also be executed using these five primitive gates as building blocks.Particularly, since the input state variables are represented as constant voltages while the output is stored as memristance, the logic operating time can be estimated as the memristance conversion time, which can be calculated by (6).Meanwhile, for better demonstrating the superiorities of the proposed logic implementation, several existing memristor-based logic circuit design approaches, i.e. memristor-aided logic (MAGIC) [27], memristor-as-drivers (MAD) logic [29], fast Boolean logic (FBL) [25], three steps (TS) logic [23], and CB logic [26], are introduced for the comparison purpose.The concrete comparative information is collected in Table 2.
From Table 2, compared to the other five logic implementation, only the circuit structure of the proposed method is fixed (i.e. the M-LUC).In other words, for existing memristor-based logic implementation, different logic operations always require different circuit structures, which may result in additional fabrication steps and costs.Meanwhile, unlike the MAGIC, MAD logic, FBL, and CB logic, the proposed method does not need to consider the design constraints (mainly referring to the voltage constraints) during the logic operation.These two advantages indicate that the proposed M-LUC is more flexible and easier to design.Furthermore, initialisation is not necessary for the proposed method, which will effectively accelerate the logic operation.Mathematically, when two time-sequence inputs with the frequency of 1/T are applied to the proposed logic circuit within the time interval of [0, NT], the output results can be obtained almost synchronously with the injection of the inputs (total time: NT), due to the fast memristance variation.For the other five methods, the total time is much longer than that of the proposed method (double or triple), because of the additional initialisation.In addition, the proposed method has the potential to constitute a compact and high-efficiency logic network for the realisation of MIMO logic operations.The specific demonstration is provided in the next section.

Memristor-based logic network
In this section, a compact memristor-based logic network is constructed, which can be deemed as an effective supplement for hardware implementation of complex MIMO logic operations.As shown in Fig. 3, the memristor-based logic network is actually developed by several fundamental M-LUCs connected in a serial or parallel configuration.The specific theoretical analyses based on these two circuit topologies are provided below.
where symbol F denotes the floating terminal, and V L = 0 V and V H = 5 V denote the logic '0' and logic '1', respectively.where N means the total cycles of the time-sequence inputs.Notably, we assume that the initialisation can be completed within a period T.

4
IET Nanodielectr.This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)LUC, and the obtained output OUT can be represented as a set of the related results of each M-LUC, namely where element out i (i = [1, l]) is the independent output of the corresponding layer (M-LUC).

Memristor-based logic network
As shown in the rightmost of Fig. 3, the logic network can be further developed by multiple series-parallel-connected M-LUCs.
For the sake of simplicity, the M-LUC is defined as the first-level component of the memristor-based logic network.The second-level compositions can be achieved by multiple first-level elements connected in series or parallel.The highest-level composition, i.e. the logic network, is constructed by multiple series-connected M-LUCs (second-level elements) connected in parallel.
Then, the overall information of the memristor-based logic network is collected in Table 3.

Design robustness considerations
Theoretically, when the proposed logic circuit is performed under the ideal condition, the obtained results are the same as the mathematical analysis.However, the noise induced by parameter variations may significantly affect circuit performance.For a TiO 2 /TiO 2 − x memristor device, the device parameter variations mainly refer to the device geometry variations [32].The geometry parameter variations resulting from the line edge roughness (LER) and thickness fluctuation (TF) may influence the electrical properties of the nanoscale device, and even the final results of the proposed logic circuit.
According to Niu et al. [32] and Hu et al. [33], the variation of the cross-section area (S) can be described by LER, and the variation of the thickness (D) can be described by TF.If taking into account the area variations, the memristance expression can be rewritten by [33] where ρ L and ρ H are the electrical resistivities of the doped and undoped regions, respectively; θ Area = S'/S represents the area variation factor; S' denotes the actual cross-section area; and S and D denote the ideal cross-section area and thickness of the memristor.
Similarly, if considering the TF impact on the memristance, the memristance expression can be rewritten as [33] where θ D = D′/D is the thickness variation factor and D′ is the actual thickness of the memristor.From ( 22) and ( 23), it is clear that the process variations of the cross-section area and the thickness influence the memristance in opposite ways.Specifically, positive cross-section area variation (θ Area >1) lead to the reduction of memristance, but positive thickness area deviation (θ D >1) results in the increase of memristance.In particular, ( 22) and ( 23) will be equivalent when θ D θ Area = 1.Under this assumption, the memristances under the cross-section area and thickness variation are illustrated in Fig. 5.
As shown in Fig. 5, the blue-solid line denotes the ideal case, the red-dashed line and the green dashed line represents the memristances suffering from the cross-section area and thickness variation, respectively.It can be seen that both variations change the ideals R H and R L into R′ H and R′ L , respectively.
To evaluate the impact of process variation on the properties of the TiO 2 /TiO 2-x memristor, we conducted Monte Carlo simulations on 1000 memristor samples.The specific device parameters are set to R 0 = 10.1 kΩ, R L = 10 kΩ, and R H = 100 kΩ.The applied voltage is V = V m • sin(2πft), where V m = 5 V and f = 0.5 Hz.The rootmean-square amplitude and the correlation length are set to the typical values, 2 and 20 nm, respectively [33].The TF is modelled to have a Gaussian distribution with a mean of zero and a deviation of 2% thin-film thickness.For the TiO 2 /TiO 2-x thin-film memristor, the minimal and maximal (±3σ) values of the electrical parameters in the percentage of the corresponding ideal values are summarised in Table 4.
From Table 4, the limiting memristances (R H and R L ) are affected in a similar way by LER and TF, which implies that θ Area and θ D have similar weight on the variations of R H and R L .In other words, the device parameter variations (i.e. the device geometry variations) may have a slight influence on the limiting memristances.In the presented logic circuit, the limiting memristances of the load memristor (R SL and R SH ) are related to the output results.To reduce the impact of the device parameter variations and increase the circuit fault tolerance, the threshold resistance M thre is suggested to satisfy R SL <<M thre <<R SH .

Computer simulations
In this section, a series of computer simulations were conducted for verification purpose.The experiment platform is a desktop workstation with Core i7-6700 processor, 16 GB DDR4 random access memory and Windows 10 operating system.For clarity, the entire experiments are divided into three parts, namely 2I1O Boolean logic operations, MI1O logic operations, and MIMO logic operations.The specific process description is provided below.

Determination of parameters
In the experiments, the specific parameter setting is provided in Table 5.where n and l denote the number of the time-sequence inputs and the layers, respectively.Actually, the M-LUC can be deemed as a special case of the logic network with n = 2 and l = 1.From Table 5, the main parameters are referring to the device parameters of the HP memristor.Specifically, R L and R H denote the boundary resistances of the memristor in the regulatory region.R SL and R SH are the boundary resistances of the load memristor.R 0 and R S0 are the initial resistances of the memristors in the regulatory region and load region, respectively.Notably, since the initialisation is no longer necessary in the proposed method, the initial memristances R 0 and R S0 have no influence on the output results.V L , V H , and V c are all constant voltages.The voltage relationship should always satisfy V H >V c >V L = 0. Parameter D is the thickness of the memristor.In addition, the threshold resistance M thre is a very important parameter that may influence the output results of the proposed logic circuit.On the basis of the robustness analysis in Section 5, M thre is set to (R SL + R SH )/2.

2I1O Boolean logic operations
As mentioned above, when the logic network is in its simplest form (i.e.n = 2 and l = 1), it is able to perform the basic 2I1O Boolean logic operations including the AND, OR, NOT, NAND, and NOR gates.The time-sequence inputs are given in Fig. 6a and the corresponding simulation results are demonstrated in Fig. 6b.Notably, the specific switch setting can be found in Section 3, and the period of the time-sequence inputs is set to T = 100 μs.
In Fig. 6b, the simulation results of the four basic Boolean logic gates (i.e.AND, OR, NAND, and NOR gates) are provided.Notably, the red-dashed line denotes the value of the threshold resistance M thre .In fact, the obtained IO relationship is consistent with the corresponding truth table, which indicates the validity and effectiveness of the proposed logic circuit.Meanwhile, since the memristance variation is sufficiently fast and the additional initialisation is no longer necessary, the correct output results can be achieved almost synchronously with the injection of the input signals.Namely, the total delay is zero, which manifests that the proposed method is effective and efficient, compared with the existing memristor-based logic implementation [18][19][20][21][22][23][24][25][26][27][28][29].

MI1O logic operations
When the number of the time-sequence inputs n is larger than two, the proposed logic network is able to realise the MI1O logic operations.For illustration purpose, the proposed logic network is utilised to perform the 8-input NAND operation in this section.According to the aforementioned description, the logic network is composed of four identical M-LUCs connected in series.The specific time-sequence inputs (In1-In8) are exhibited in Fig. 7a and the corresponding outputs are exhibited in Fig. 7b.
In Fig. 7b, the black-solid line denotes the logic output (i.e. the load memristance) of the 8-input NAND operation.Similarly, the red-dashed line denotes the threshold resistance M thre .Specifically, during the first cycle 0-100 μs, all the inputs are kept in the high level (i.e.Ini = V H = 5 V, i = [1,8]), the load memristance increases to its maximum value R SH rapidly (R SH >M thre ) which represents the logic '0'.Then, the time-sequence input In1 (the red-solid line) changes to the low level (i.e.In1 = V L = 0 V) before the start of the second cycle.The load memristance suddenly decreases to its minimum value R SL (R SL <M thre ) which denotes the logic '1'.Furthermore, during the rest of the time 200-900 μs, there exists at least one low-level input voltage V L = 0 V, and the load memristance remains unchanged, i.e. the lowest memristance R SL .It is smaller than the threshold resistance M thre , which represents the logic '1'.Clearly, the time-sequence inputs and the generated load memristance curve (output) jointly indicate that the proposed logic circuit is able to perform the MNAND operation.
Similarly, the series-connected M-LUCs can be used to realise other MI1O logic functions such as MAND, MOR, and MNOR.The specific realisation process will not be repeatedly provided in this section.

MIMO logic operations
As the aforementioned description, the proposed logic network has the potential to realise MIMO logic operations.For verification, a compact logic network with three time-sequence inputs and four layers is developed for the implementation of the three-input-fouroutput logic operation.Notably, the four layers are responsible for the realisation of three-input AND, NOR, OR, and NAND operations.According to (21), the final output can be expressed as a set of the results of the above four logic gate operations, i.e.OUT = {AND, NOR, OR, NAND}.Concretely, three time-sequence inputs with the period of T = 100 μs are shown in Fig. 8a and the corresponding simulation results for each layer are exhibited in Fig. 8b.On the basis of the comparison between the truth tables and the obtained IO relationships, the proposed logic network is able to perform the three-input-four-output logic operations.Unlike the single-layer logic network (i.e. the M-LUC), the four different logic gate operations can be carried out simultaneously due to the parallel network structure.In other words, the proposed logic network enables the implementation of four different logic operations within a single cycle.

Conclusions
In this paper, the memristor-based Boolean logic implementation is investigated.Specifically, an M-LUC synthesised by six memristors and several switches is proposed in this work, where the input state variable is constant voltage and the output is the resistance of the load memristor.According to the different switch settings, the basic AND, OR, NOT, NOR, and NAND operations can be flexibly performed.Notably, since the additional initialisation is not necessary for the proposed method, the total delay can be effectively reduced, especially for time-sequence inputs.As a fundamental element, the proposed M-LUC is further utilised to constitute a compact memristor-based logic network with the series-parallel configuration.Meanwhile, the presented logic network has been proved to be an efficient tool for the realisation of different MIMO logic operations.Finally, a series of computer simulations are conducted to verify the effectiveness of the entire scheme, the corresponding experimental results with reasonable performance analysis demonstrate the advantages of the proposed logic network in terms of the high efficiency, low operating cost, as well as the sufficient accuracy.

Fig. 5
Fig. 5 Memristance under the cross-section area and thickness variation

Fig. 6
Fig. 6 Simulation results of 2-inputs logic operations (a) Two specific time-sequence inputs, (b) Corresponding simulation results of AND, OR, NAND, and NOR gates

Table 1
Summary of the five fundamental Boolean logic gates

Table 2
Comparison of the proposed memristor-based logic circuit with other logic implementation

Table 3 Overall
information of the proposed memristor-based logic network

Table 5 Technical
parameters of the simulations Parameters Value Parameters Value