Binary decision diagram ‐ based synthesis technique for improved mapping of Boolean functions inside memristive crossbar ‐ slices

Memristors are two ‐ terminal nano ‐ electronic devices that make it possible to design non ‐ volatile memory and logic circuits with high integration density. The logic operations of memristor ‐ based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functionshas beenreported,where aninput Booleanfunctionis firstrepresentedas a Binary Decision Diagram (BDD), followed by the mapping of the BDD ‐ nodes (netlists of 2 ‐ input NOR and NOT gates) inside a cluster of sliced crossbar ‐ arrays. The authors propose to map the BDD ‐ nodes for any input Boolean function to the crossbar ‐ slices using an improved technique, where each BDD ‐ node is mapped more efficiently, and the node ‐ logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping ‐ based realization of a BDD ‐ node has superior performance and energy ‐ efficiency than the existing IMPLY and MAGIC ‐ based BDD ‐ node designs techniques, provided all three node ‐ designs are implemented inside the similar ‐ sized crossbars. Comparative ‐ study of the synthesis results showed that the memristive ‐ circuits generated


| INTRODUCTION
The history of memristor origins back in 1971, when Leon Chua first theoretically proved its existence [1]. The memristor is a two-terminal, non-linear, fundamental passive circuitelement that relates the time integral of current with the time integral of voltage. However, the device did not receive much attention till 2008, when a team of researchers led by Stanley Williams at the HP Labs first experimentally demonstrated the physical realization of such a device [2,3]. The research team from HP Labs presented a solid-state physics-based model for the device that comprised of-a thin layer of titanium dioxide (TiO 2 ) sandwiched between two platinum electrodes. The TiO 2 layer consisted of two regions-one undoped and another doped (with slight depletion of oxygen atoms). The team experimentally observed that the resistance of such device changes with the alteration of the voltages applied across the device terminals. Also, the device was found to retain its most recent resistance value (memristance) when the applied voltage resources were removed. Soon, it was found that the memristors are actually non-volatile resistive-devices that can act as memory elements. Since then, memristors have been extensively explored for logic designing [4][5][6], as also, for the logic-realizations inside the memristive-memories [7,8].
Two logic families that mostly predominate the basis of the in-memory computing are-the material implication (IMPLY) [7] and Memristor Aided loGIC (MAGIC) [9] design styles. Following this, different synthesis techniques have been reported in the literature for in-memory logic realization using memristors [10][11][12][13]. It is observable from the existing works [6,8,12] that the circuits implemented using MAGIC-style are more energy-efficient than those realized using the IMPLY-technique. Besides, unlike IMPLY [7], MAGIC-based computations [8] do not need additional hardware (resistors). Moreover, the usage of different memristors for input(s), output makes MAGIC more favourable for in-memory computing. In this work, as also in some of the earlier works ( [10,11,13]), Binary Decision Diagrams (BDDs) have been explored as the basic data structures for in-memory logic realizations. This has been done as BDDs are well-known for efficient designing of transition systems [14], and for making the testing process convenient (for specific faults) [15]. Also, the BDDs are known for providing compact representations for many of the Boolean functions [13].
Recently, in Ref. [13] the concept of slicing crossbar-architectures has been reported. In Ref. [13], an input Boolean function is first represented as a BDD using the CUDD package [16]. Then starting from the primary-level of the BDD, all the nodes in any BDD-level are mapped simultaneously inside a cluster of sliced crossbar-arrays, while ensuring that a single BDD-node is mapped inside a single crossbar-slice. A memory processing unit (MPU)-controller [17,18] is supposed to send the necessary control signals to all the involved crossbar-slices, such that the required operations can get executed [13]. The mapping process was conducted inside the crossbar-slices in Ref. [13] mainly with the three intentions-firstly, the relatively better controllability of the sneak path issue in the smaller crossbar-slices [8,13,19,20]. Sneak path [21][22][23][24] is a disturbing issue in memristive-crossbar based computations that often leads to the erroneous sensing of the logic state of a memristor (specifically the effect becomes prominent while reading logic '0', that is, the high resistance-state of the device). The various solutions as reported in the literature ( [21,22,[25][26][27][28]) can be used to handle the sneak path problem. Secondly, the larger the crossbar-array size, the more the inactive memory-element isolation is needed to avoid the write disturb ( [8,29]) and undesired computations [8]. Such write disturbs and unwanted computations can change the content of some of the memristors during the in-memory operations, which is not desirable. In order to mitigate such adverse scenarios, one needs to apply half-select, isolation voltages to the unselected memristors in the crossbar-array ( [8,30]) to continue the seamless logical executions inside the memristive-memories. And invariably, as the count of the inactive-memristors in the array increases, the energy-cost related to the isolation of such memristors will be more [13]. A smaller crossbar-slice size is therefore used in Ref. [13] to reduce the energy cost for isolation purposes. Thirdly, in the case of sliced crossbar architecture [13], as the crossbar-array size is reduced, thus the design-complexity of the MPUcontroller ( [17,18]) is expected to get simplified [13]. In Ref. [13], three different sets of crossbar-arrays with varying-sizes were used-for the BDD node-logic implementations, for storing the intermediate BDD-level results, and for the related NOT executions. Both the size and count of the involved crossbararrays were highly dependent on the multiple cost metrics of the BDD-for any input benchmark function (e.g. node-count, levelcount, maximum number of nodes and maximum number of complemented-edges among all the BDD-levels) [13]. Whereas in the proposed work, the size of the involved crossbar-arrays is fixed; only the count of the involved slices is a function of the maximum node-count and maximum complemented edgecount among all the levels of the BDD-for any input benchmark function.
The mapping-process inside the sliced crossbar-arrays [13] differs from the contemporary mapping-techniques in [8,[10][11][12] where the nodes in any particular level of the AIG ( [8,12]) or BDD ( [10,11]) (for any input Boolean function) are simultaneously mapped in the different rows of the crossbararray (a set of such component crossbar-arrays comprise the memristive-memory [31]). However, the number of nodes mapped per crossbar-array may vary depending upon the component crossbar-array size, and the availability of the freerows inside each of such crossbar-arrays. In Ref. [31], it was reported that the sizing of each component crossbar-array is done based on the fact that -the memristor, located inside the crossbar at the farthest distance from the voltage-resources, should at least receive the threshold voltage to perform the switching operations during the in-memory computations. Of course, the designer can fix the switching delays, and that too decide the component crossbar-array size. Both the row-based mapping process ( [8,[10][11][12]), and the slice-based mapping technique [13] have their individual pros and cons.
The row-based mapping techniques in [8,[10][11][12] use relatively larger crossbar-array size, and therefore, reduce the hardware footprint of the peripheral circuits required. Also, the possibility of the locality of the operand-data within the same crossbar-array is relatively higher at the time of the in-memory operations [31]. However, as the crossbar-array size increases, the feasibility of more number of memristors to get affected by the write disturb/undesired-computations, and the sneak path issues [8,[21][22][23][24]29] will be there. As discussed earlier, the energy cost for the isolation purposes will therefore be more for the larger crossbar-arrays [13]. Besides, the higher complexity of the control circuit's design is also an issue for the larger crossbar arrays [13]. On the other hand, in the case of sliced crossbar-architectures [13], as each of the involved crossbar-array size is kept minimum, thus there will be a necessity for more peripheral circuits, and the chances of outside-crossbar communications may increase at the time of the in-memory computations. However, as the inactive Memristor-Count (MC) gets reduced for the computations inside the crossbar-slices, as compared to that for the larger crossbar-arrays in the state-of-the-art synthesis works [8,[10][11][12], thus lesser number of memristors will be affected by the write-disturb, unwanted logic-operations, and sneak path problems during the in-memory computations. And this implies a nominal energy consumption for the isolation purposes [13]. Also, the controller design becomes simpler due to the relatively smaller size of each of the crossbar-slices [13]. As the primary goal of this work is to map the input Boolean functions efficiently inside a cluster of crossbar-slices, thus the complexity of the MPU-controller has not been analysed in the present work. However, any of the existing controller-designs reported in [17,18,32] can be used to serve the purpose.
Inspired by the recent works [13], we present an improved synthesis technique that employs a more efficient mapping for each BDD-node. The node-design has been implemented CHAKRABORTY ET AL.
following the MAGIC design style. The results of our proposed MAGIC-based BDD-node mapping has been found to outperform the mapping-results for the existing IMPLY, MAGIC-based node designs ( [10,13]), both in terms of speed and energy-efficiency, provided all the node-designs are mapped inside the similar-sized crossbar-slices. Finally, our proposed mapping for a single BDD-node is utilized to map all the BDD-nodes for any input Boolean function, inside a cluster of the sliced crossbar-arrays. The methodology for our proposed synthesis technique has been described in detail in the subsequent sections.
The rest of this paper is organized as follows. In Section 2, IMPLY [7] and MAGIC [9] design styles are discussed. In Section 3, our proposed MAGIC-based mapping for a BDDnode inside a crossbar-slice is presented. Then the results of the proposed mapping are compared with the mapping-reports for the existing IMPLY and MAGIC-based node-designs [10,13] in terms of Step-Count (SC), MC, and the energy required. Section 4 presents an improved BDD-based synthesis technique that can be used for mapping of the BDD-nodes (for any input function) inside a cluster of memristive crossbarslices. In Section 5, circuit performance, hardware footprint and energy-efficiency of our approach are compared with the existing works in [10,11,13]. Finally, we conclude in Section 6.

| PURE-MEMRISTIVE DESIGN METHODOLOGIES
In the following subsections, brief descriptions of the two most prominent design styles followed for in-memory computing, that is, IMPLY [7] and MAGIC [9], are presented.

| Memristor-based IMPLY logic
In the case of memristive-logic operation using IMPLY [7], two memristors X and Y are involved such that X→Y (X IMPLY Y) ¼ ¬XVY. Both IMPLY and FALSE operations (where the FALSE operation always results in logic value 0) together constitute a complete logic computation set that can be utilized to implement the logic of any Boolean function.
In Figure 1, IMPLY-operation inside a 1 � 2 crossbararray is shown, where the two memristors X and Y, and a resistor R G participate in the operation. The value of R G lies between {R ON , R OFF } [7], where R ON and R OFF are the resistance values for the memristors in on (set) and off (reset) states, respectively. At the time of IMPLY-operation, two voltages V SET and V COND (V COND < V SET ) [7] are used. V COND is applied to the column corresponding to the memristor X, and V SET is applied to the column corresponding to the memristor Y. Finally, the result of the IMPLY-operation, that is, X→Y (X IMPLY Y), is written on to the Y memristor.
So, the content of one of the input memristors is overwritten at the end of the IMPLY-operation. The results of the corresponding IMPLY-operations are shown in Table 1 (see Ref. [7] for details). It is to be noted that to write logic '1' or '0' in the desired memristor, set or reset voltages (V SET or V RESET ) are applied to one of the terminals of the device, whereas the other terminal is connected to ground [8].

| MAGIC design methodology
In the case of MAGIC [9] design style, an n-input MAGIC-NOR/NOT (a subset of MAGIC-NOR with n ¼ 1) operation is conducted inside the memristive-crossbar using the execution voltage V EXE . For row-based MAGIC-operation, V EXE is applied to the column(s) corresponding to the input memristor (s), and the column for the output memristor is connected to ground (GND) [8]. See Figure 2a for a row-based n-input MAGIC-NOR operation inside a 1 � (n þ 1) crossbar-array. Reverse in done for the column-based MAGIC-NOR/NOTexecution [8]. The row(s) corresponding to the input memristor (s) are grounded, and the row for the output memristor is connected to V EXE . Please refer to Figure 2b for a column-based n-input MAGIC-NOR operation inside a (n þ 1) � 1 crossbararray. It is to be noted that for MAGIC-based executions the F I G U R E 1 IMPLY operation using memristors output memristor is previously kept in set condition (see Ref. [9] for details). The content of no input memristors is overwritten at the end of the MAGIC-operation, unlike IMPLY. Also, only memristors participate in MAGIC-operations.

| PROPOSED AND EXISTING MEMRISTIVE-MAPPINGS OF A BDD-NODE, DESIGNED USING IMPLY AND MAGIC STYLES
In this section, both the existing and proposed mappings for a BDD-node inside a crossbar-slice are discussed that utilize IMPLY and MAGIC design styles. The functionality of each BDD-node is equivalent to that of a 2:1 multiplexer (MUX), which comprised of three 2-input NOR gates and four NOT gates in Ref. [13]. In Figure 3, an improved gate-level design for a 2:1 MUX is shown that comprises of three 2-input NOR gates and one NOT gate. In Ref. [13], the MAGIC-based realization of the NOR/NOT-netlist for a BDD-node was utilized for the mapping of a BDD-node inside a 3 � 3 crossbar-slice. Subsequently, all the nodes in any BDD-level were simultaneously mapped inside a cluster of 3 � 3 crossbar-slices. The condition of mapping being one BDD-node has to be mapped inside each 3 � 3 crossbar-slice [13]. Both the gate-level designs for a BDD node logic-as exhibited in Figure 3 and that reported in Ref. [13], comprise of 2-input NOR and NOT gates. In Ref. [13], as also in this work, the size of a crossbar-slice for BDD-node implementation has been selected as 3 � 3, as this is the minimum array-size that is needed to accommodate both the single-row and single-column based 2-input MAGIC-NOR operations. Tables 2-4 exhibit the steps related to the memristivemapping of a single BDD-node inside a 3 � 3 crossbar-slice. The BDD node-designs as used for the mappings in Tables 2-4, refer to the existing IMPLY-design for 2:1 MUX in Ref. [10], MAGIC-design for 2:1 MUX reported in Ref. [13], and the MAGIC-NOR/NOT based realization of our improved 2:1 MUX-design in Figure 3, respectively. In Ref. [13], during the mapping of a BDD node-logic inside a 3 � 3 crossbar slice, instead of performing three MAGIC-NOT operations for the inputs {A, B, S}, the inverted values of {A, B, S}, that is, {A', B', S'}, were directly written in the relevant memristors inside the crossbar-array (see Table 3). However, unlike Ref. [13], in this work, we only directly write S′ in the respective memristor inside Rewrite location of A with the content of memristor X Content of X at (1,3) is written to the location of A, that is, (2,1) the 3 � 3 crossbar, instead of performing MAGIC-NOT (S) at the time of mapping of each BDD-node (see Table 4 and Figures 3 and 4a). In Table 5, the memristive-designs of 2:1 MUX in [10,13] and that in Figure 3 are compared, where the designs are implemented following the existing/proposed-mapping steps in Tables 2-4, respectively. The results of the different MUXmappings are compared in terms of necessary computation SC, involved MC, and the energy required for the implementationpurposes. The IMPLY and MAGIC-designs of the 2:1 MUX are simulated inside 3 � 3 crossbar-arrays where the interconnect resistance (R wire ), and capacitance (C wire ) as used between each pair of adjacent nodes of the crossbar are assumed to be of 1.25 Ω, and 0.01 fF, respectively [28]. In this work, all the simulations are conducted assuming the memristors to be the bipolar Resistive-RAM devices. For the simulation purpose, VTEAM memristor model reported in Ref. [33] is used along with the Biolek's window function [34], and the simulations are run in Cadence Virtuoso (version 6.1.6). Table 6 shows the VTEAM-model parameters [33] as used in this work. In Table 6, x symbolizes the dynamic state variable of a memristor [33]. {x on , x off } bound x within the device dimensions, that is, {0 to 3} nm in this case. V T,on , V T,off represent the setthreshold, and the reset-threshold voltages respectively. Here, α on , α off , k on and k off are constants. The VTEAM-model parameters in Ref. [33] (see Table 6) produce a switching delay of 1 ns when set, reset voltages of magnitudes V SET ¼ 2 V, V RESET ¼ 1 V are applied across the model, respectively. This model has been reported to provide a good fit for the fabricated memristive-devices [35].
For MAGIC-NOR/NOT, V EXE of magnitude 1.5 V is used, and a maximum delay of 3.02 ns is observed for MAGIC-NOT (1) [36]. IMPLY operations are performed with V COND ¼ 1.5 V, V SET ¼ 2.12 V and R G ¼ 1.5 KΩ [7]. Set (V SET ), and reset (V RESET ) voltages are of magnitudes 2 V and 1 V, respectively [8]. For fair comparisons among the different IMPLY and MAGIC-based MUX-realizations, the 2:1 IMPLY-MUX design reported in Ref. [10] is mapped inside a 3 � 3 crossbar-slice (ref. to Table 2). This has been done, as the same-sized crossbars have been used in Ref. [13], as also in this work, for the MAGIC-based mappings of the 2:1 MUX-designs (see Tables 3 and 4; Figure 3). To estimate the energy for a particular MUX-design, at first, the energies for its constituent micro-operations are determined. To evaluate the energy for a particular micro-operation say for MAGIC-NOT, the energy is calculated for the different input-combinations, that is, 0, 1 for a NOT-gate. Finally, the energies for all the different input-combinations are averaged to find out the energy for that specific micro-operation [8]. The energies for all such constituent micro-operations relevant to any specific MUX-design Read out the content of G4

Write A and B
Read out the content of G3 G3 ¼ (3,3) Note: Mapping steps for the MAGIC-MUX [13] (see Table 3) does not include the step for the write operation in the buffer crossbar, as in Ref. [13]. The modifications are done as per the requirements of the present work.

-
are summed-up, to estimate the energy required for that particular design implementation (see Table 5).
In this work, a read voltage (V READ ) of magnitude 0.9 V has been applied for a duration of 330 ps to read the data stored in a memristor. Thereby, the time to identify the logic states '1' and '0' are found to be 9.41 ps, and 72.15 ps, respectively [28]. Energy to recognize logic states '1' and '0' are found to be 4.71 fJ, and 0.01 fJ, respectively. Additional delay and energy will be needed for logic identification, based on the type of sense-amplifier [37][38][39] used for the logic-sensing purpose.
From the comparisons in Table 5, it is observed that the memristive-design of a 2:1 MUX, implemented using our proposed MAGIC-based mapping, is more improved in performance (by 45.45% and 14.29%, respectively) and energy-efficiency (by 58.21% and 8.13% respectively) than its peers, realized using the mapping of the existing IMPLY and  Table 4, (b) Step 3 in Table 4, (c) Step 4 in Table 4 and (d) Step 5 in Table 4. The magnitudes of V ISO (i.e. isolation voltages) for write operation (steps 2, 3, 4 and 8 in Table 1; steps 2 and 3 in Tables 2 and 3) and logic-execution (steps 5, 6, 9 and 10 in Table 1; steps 4, 5 and 6 in Table 2; steps 4 and 5 in Table 3) are selected as per their respective definitions in [7,8]

| IMPROVED LOGIC SYNTHESIS USING EXISTING/PROPOSED MEMRISTIVE-MAPPINGS FOR THE BDD-NODES
In the following subsections, the steps related to the improved synthesis approach are described. The block-diagram representation for the same is shown in Figure 5. The techniques to estimate the various evaluation metrics like SC, MC and the energy required for the in-memory implementation of an input Boolean function are also explained.
(1) At first, the input benchmark function is fed to the CUDD package [16] in PLA file format. Using CUDD programming, then the BDD network corresponding to the input function is generated. In the present work, the Reduced Ordered BDDs (i.e. the ROBDDs) are referred to as the BDDs. (2) The BDD network thus generated is then traversed in a level-wise manner, and the relevant cost metrics related to the graph (node-count, level-count, etc.) are extracted. (3) After this, the scheduling algorithms ASAP (As Soon As Possible), ALAP (As Late As Possible) and RC (Resource Constrained) [40] are applied to schedule the execution of the BDD-nodes, based on the input-dependencies, and a target to achieve a minimum critical-path delay for the BDD using a minimum number of nodes per BDD-level. Subsequently, the cost metrics related to the node-scheduled BDD are re-extracted (please refer to Table 7). (4) Finally, all the nodes in any BDD-level are simultaneously mapped inside a cluster of 3 � 3 crossbar-slices for their further computations (please refer to Tables 2-4; Figure 6).
Unlike Ref. [13], no separate crossbar-slice with different array-size has been used in this work for the NOT-executions corresponding to the complemented-edges in the BDD. In addition, we propose to remove the extra write-steps to write the MUX-outputs in the buffer crossbar-array (for details, see Ref. [13]). The concept being: two particular memristors (memory-addresses) inside the memristive-crossbar are initially reserved to store logic '1' and logic '0' data. Once the required memristive-operations for the BDD-nodes at any level are completed, the output data are read from all the relevant memristors in the 3 � 3 crossbar-slices, as these data are needed to set-up the {A, B}-inputs of the MUXes (please refer to  in the successive BDD-levels. Based on the readdata for the MUX-outputs (either '1' or '0'), initially reserved addresses for logic '1' and '0' can be used as the addresses for the inputs of the MUX-operations (i.e. for A and B) in the successive non-consecutive BDD-levels, wherever it is needed. And at the time of the MUX-computations in the successive levels, whenever the MPU-controller ( [17,18]) detects these known-addresses, the controller is assumed to send the suitable control signals to the select lines of the analog-multiplexers (attached to the rows and columns of the memristive-crossbar [18]) such that the desired logic-states ('1' or '0') are set for the input memristors of the related MUXes (i.e. steps 3 and 4 in Table 2, and Step 3 in Tables 3 and 4).
Once the read-operations for the BDD-node outputs at any level are over, if an outgoing complemented edge is detected for any BDD-node, then the 3 � 3 crossbar from which the BDD node-output is coming out is treated as the base-crossbar for performing the related NOT-operation. Doing this, no additional write-step is required to write the NOT-input data in any other specific crossbar-array, unlike the works in Ref. [13]. The free-memristors in the involved 3 � 3 crossbar-slices can be treated as the output-memristors for the related NOT-operations. These free-memristors (e.g. the memristors at loc. (3,2) for the IMPLY-based MUX-mapping in Table 2, loc. (3, 1) for the MAGIC-based MUX-mapping in Table 3, locs. (3,1) or (3,2) for the proposed MAGIC-based MUX-mapping in Table 4, Figure 4) are already initialized to reset/set states during the IMPLY/MAGIC-based MUX-realizations inside the crossbar-slices. The step for the IMPLY/ MAGIC-NOT evaluation in a BDD-level can be overlapped with Step 1 of the MUXes in the successive level (see Step 1 in  Tables 2-4). And the step to read the NOT-output can be overlapped with the Step 2 for the MUXes in the successive level (see Step 2 in Tables 2-4). Finally, if any outgoing complemented edge is found to exist for the topmost BDD-level (containing any of the root-nodes for the output functions), then two additional steps are required for the corresponding

Max_ OCE_L Tot_CE Top_L_OCE
Step-count   -119 NOT-operation(s): step for NOT-evaluation(s) and step for reading the output of the NOT-operation(s).
The evaluation metrics, that is, the no. of 3 � 3 crossbarslices, steps, memristors, and energy required for the memristive-realization of an input benchmark function inside a cluster of 3 � 3 crossbar-slices using our improved synthesis technique are given as follows:  Table 7). //extra 2 steps for topmost BDD-level, containing root node (s) with outgoing complemented edge (s).

| EXPERIMENTAL RESULTS AND DISCUSSION
In this section, a comparison is conducted for the memristiverealizations of a set of different benchmark functions, where the results of our improved synthesis technique are compared with that of a recently reported work in Ref. [13] that also used the concept of slicing crossbar-architecture.
In order to obtain the results for the proposed technique, each benchmark circuit is implemented separately using the memristive-mappings for the IMPLY-MUX (steps in Table 2), MAGIC-MUX (steps in Table 3), and our proposed MAGICbased mapping for the efficient MUX-design in Figure 3 (steps in Table 4). Finally, all these results are compared in terms of MC, SC and the energy required. The results of our work are not compared with the existing contemporary works [8,12] that used AIGs as the data structure for the memristive-circuit designing. The reason being first, the present work emphasizes on memristive-logic realizations using BDDs, the context being the easier testability for the BDDs using 2:1 MUXes as the BDDnodes [15]. Secondly, the existing AIG-based synthesis works [8,12] did not use the slice-based mapping approach, as followed in the present work and the existing works in Ref. [13]. Therefore in this work, the comparison is conducted with the results of the most recently reported-related works in Ref. [13], to exhibit the improvements achieved by using our proposed slice-based mapping process inside a cluster of 3 � 3 crossbars.
A family of different benchmark circuits ( [41], [42]) are implemented following our proposed technique (that use the individual memristive-mappings for the 2:1 MUX, as given in Tables 2-4 respectively), and the corresponding results are compared with the synthesis reports in Ref. [13]. The related comparative study is shown in Table 7. In Table 8, the results of our proposed work are compared with that of the existing BDD-based works in [10], [11]. It is to be noted that the steps, MCs shown in Table 8 for [10,11], exhibit the results for the logic-computations only, and do not include the additional steps, memristors (for copy) required for the data-arrangement (read-write/copy) purposes. For logic-implementations using (a) (b) F I G U R E 7 Binary decision diagram (BDD) for con1 (a) before node-scheduling, as generated using CUDD [16] and (b) after node-scheduling [40]. In this work, the edges for (!1) are assumed to come from the primary input 0, and, thus the edges for (!1) are not counted under the complemented edges (Dotted-edges in Figure 7a,b). Separate memristors (memoryaddressess) have been reserved in this work to store the primary input values, that is, logic '1', '0'. ** Abbreviations used in this work: Tot_NCtotal node-count; Tot_LCtotal level-count; Max_NC_Lmaximum node-count among all the levels; Max_OCE_Lmaximum outgoing complemented edge-count among all the levels, without repetition; Tot_CEtotal complemented edge-count in the BDD, without repetition; Top_L_OCEindex to indicate the presence of outgoing complemented edge(s) in the topmost BDD-level