On the applicability of two ‐ bit carbon nanotube through ‐ silicon via for power distribution networks in 3 ‐ D integrated circuits

This study investigates the possibility of the carbon nanotube (CNT) ‐ based through ‐ silicon vias (TSVs) for improving power integrity of 3 ‐ D integrated circuits (3 ‐ D ICs). The circuit model is developed for 2 ‐ bit CNT TSV and validated through the full ‐ wave electromagnetic simulator HFSS simulations. The 2 ‐ bit CNT TSV is applied to power distribution networks (PDNs) by combining the validated equivalent ‐ circuit model and that TSV ‐ based PDN impedance is compared with the traditional one. By virtue of the large capacitance and low inductance of the 2 ‐ bit CNT TSV, the PDN impedance of the 3 ‐ D IC can be suppressed significantly and the anti ‐ resonant frequency can be increased.


| INTRODUCTION
3-D integrated circuits (3-D ICs), as a promising solution to keep pace with the scaling of Moore's law, have aroused interests from researchers worldwide [1,2]. Compared with conventional 2-D ICs, 3-D ICs can provide enormous advantages in high density, multifunction and heterogeneous integration by stacking chips vertically. To promote the development of 3-D ICs, through-silicon via (TSV), as the key technology connecting chips directly through the substrate, has been investigated extensively in the past decade [3][4][5].
Although TSVs can significantly reduce the interconnect length and improve the system bandwidth, they would induce high upper impedance peaks, which may be the simultaneous switching noise generators integrated circuit power distribution network (PDN) [6,7]. To suppress the TSV inductance effect, the power/ground (P/G) vias should be placed as close as possible [8]. However, to guarantee the yield, the holes should be etched uniformly. To date, different TSV array arrangements and decoupling capacitor techniques have been explored to resolve the power integrity issues [9][10][11][12][13][14]. Furthermore, to reduce the burden of on-die decoupling capacitors, an n þ contact surrounding the power TSV was proposed to enhance its parasitic capacitance at high frequencies [15].
analysis [19]. However, the influence of the CNT kinetic inductance is neglected in previous study of 2-bit CNT TSVs [2]. To resolve this issue, the modified equivalent-circuit model of 2-bit CNT TSV is proposed, as shown in Figure 1b, with the consideration of the CNT kinetic inductance. The related geometrical parameters are listed in Table 1.
The mutual conductance can be further suppressed by introducing semiconducting CNTs in the middle [20]. Two parts of CNT forests are metallic, and serve as power and ground vias. The circuit model of the 2-bit CNT TSV is presented in Figure 1b, where the mutual capacitance between P/G vias is given by where ε denotes the effective permittivity of medium between P/G vias. R and L represent the effective resistance and inductance of the 2-bit CNT TSV, and they can be obtained using the partial-element equivalent-circuit method [21]. As shown in Figure 2, the circuit model is verified against the HFSS simulation results with a good agreement observed. In the simulation, the TSV filling conductor and the middle medium are assumed as Cu and SiO 2 as CNTs are unable to simulate in HFSS. Figure 3a shows the schematic of on-chip grids, and its size is 1.03 � 1.03 � 0.02 mm 3 . The on-chip grids are embedded in a 1.09 � 1.09 � 0.06 mm 3 inter-dielectric layer. The power and ground wires are arranged alternatively to reduce the PDN impedance, with other geometrical parameters presented in Table 2. According to the location, the on-chip grids can be decomposed into three types of unit structures, that is, corner, edge and inner units, as shown in Figure 3b. The unit structures can be characterized as the circuit model in Figure 3c by substituting the geometrical parameters into the extraction of circuit elements. The series resistance of the wire can be calculated as where W, H and l denote the width, thickness and length of the wire, respectively, σ is the conductivity, μ 0 is the permeability in vacuum and f is the frequency. As the power and ground wires are arranged alternatively, the series inductance is given as F I G U R E 2 (a) S 11 and (b) S 21 parameters of the 2-bit carbon nanotube through-silicon via. The geometry is as follows: where the self-and mutual inductances are calculated by ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi ffi P is the distance between adjacent P/G wires. The capacitance C OA can be obtained by Cheng et al. [13].
where the capacitance between the upper power (ground) wire and bottom ground (power) wire and the wall-to-wall capacitance are calculated by By virtue of the circuit model of the unit structures, the complete model of the on-chip grids can be obtained. According to the ports in Figure 3a, the magnitudes of Z-parameters are obtained and depicted in Figure 4. It is evident that the circuit model results agree well with the HFSS simulation results. In general, the parasitic effects  between on-chip grids and TSVs are negligible, and the impedance of the whole 3-D IC PDN can be obtained by combining the models of on-chip grids and TSVs [13]. In this way, the PDN impedance of the whole structure shown in Figure 5a can be obtained and compared with the simulated results (see Figure 5a,b).

| RESULTS AND DISCUSSION
Based on the circuit models, the 3-D IC PDN based on 2-bit CNT TSVs can be investigated. Here, it is assumed that the CNTs are single-walled CNTs with identical diameter, and they are closely packed in the via. The semiconducting single-walled CNTs are in the middle to prevent lateral conduction, while the metallic CNTs are connected with the pads to provide conduction path. The effective complex conductivity of the CNT bundle is employed by Zhao et al. [17]. where D is the CNT diameter, δ ¼ 0:34 nm is the distance between adjacent CNTs, and Z CNT is the self-impedance of an isolated single-walled CNT, that is, where R mc denotes the imperfect contact resistance and is neglected as it highly depends on the fabrication process. N ch ¼ 2 is the number of conducting channels, and λ ¼ 1000D is the effective mean free path. h is the Planck's constant, q is the electron charge, v F is the Fermi velocity and ω is the angular frequency. The relative permittivity of the CNT forest is adopted as 36 according to Liu et al. [22]. F I G U R E 6 (a) Schematic of 3-D integrated circuit power distribution networks with a pair of power/ground through-silicon vias (TSVs) and a pair of 2-bit carbon nanotube (CNT) TSVs, and its (b) Z 11 and (c) Z 21 parameters. The TSV pitch is 100 µm, while the other geometrical parameters are same with those used for producing Figure 5 As the 2-bit CNT TSV can assemble the power and ground vias in one hole, it has much smaller inductance than conventional TSV pair. Moreover, its large mutual capacitance between the P/G vias can provide timely and effective power to nearly transistors, thereby producing a low impedance path to high-frequency signals. To validate the related, a set of two-stacked chip-PDNs connected by a pair of P/G Cu-filled TSVs is studied, as shown in Figure 6a. For easy of comparison, the hole size is kept unchanged, while the CNT forests are inserted into two holes to form a pair of 2-bit CNT TSVs. Figure 6b,c compares the PDN impedances in two cases, and it is evident that the implementation of 2-bit CNT TSVs can not only significantly suppress the impedance, but also put forward the anti-resonant frequency. It is worth noting that large capacitance and small inductance possessed by such 2bit TSV are oriented from its unique structure. The benefits of suppressing the PDN impedance can also be achieved by using Cu as the filling conductor. However, it would be difficult to implement such 2-bit TSV using Cu as it is not an anisotropic material, while further effort is required in future to investigate fabrication process of such 2-bit SWCNT-based TSVs.
Finally, the influence of the 2-bit CNT TSV density on the PDN impedance is investigated. As shown in Figure 7a-c, three cases of TSV arrays are considered, and it is evident that with the increasing number of TSVs, the capacitance would be increased significantly, whereas the resistance and inductance are reduced [6]. As shown in Figure 7d, both the PDN impedance and the upper peak are reduced dramatically with the increasing TSV density.

| CONCLUSION
Although TSVs can enable 3-D heterogeneous integration, the TSV inductance effect would produce high upper peaks of PDN impedance. To improve the power integrity, the 2-bit CNT TSVs were employed in the 3-D IC PDN applications. The large capacitance of the 2-bit CNT TSV can provide timely and effective current and power to devices nearly, thereby reducing the burden of on-die decoupling capacitors.  Moreover, the mutual inductance between power and ground vias in a 2-bit CNT TSV can effectively reduce the total inductance. It was demonstrated that 2-bit CNT TSVs can not only suppress the PDN impedance, but also increase the antiresonant frequency, indicating that the implementation of the 2-bit CNT TSVs would be helpful for improving the power integrity of the 3-D ICs.