Analytical model and simulation ‐ based analysis of a work function engineered triple metal tunnel field ‐ effect transistor device showing excellent device performance

In this study, the authors propose a work function engineered (WFE) triple metal (TM) tunnel field ‐ effect transistor (TFET) device, which exhibits lower subthreshold slope (SS) and better on to off current ratio in comparison with conventional double gate TFET and dual metal TFET device. An analytical model is formulated to study the performance of the proposed device. A simulation ‐ based study of these TFET devices has been carried out with the help of 2D TCAD (Technology Computer Aided Design) Sentaurus device simulator for different channel length values in order to validate our proposed mathematical model. The source side n þ pocket in the proposed triple metal (TM) TFET device enhances tunnelling probability thus increasing on current and off current is controlled by another n ‐ pocket near drain side. Significantly lower subthreshold slope (less than 10 mV/decade), high transconductance (in the order of 10 (cid:0) 4 S/μm), low energy ‐ delay product (24.601 fJ ‐ ns/μm) obtained for TM WFE TFET makes this device more suitable for digital logic and RF (Radio Frequency) application.


| INTRODUCTION
Tunnel field-effect transistor (TFET) has become a promising and potential device for use in low power application. TFET may act as a possible alternative of metal oxide semiconductor field effect transistor in very large scale integration circuit because of its excellent immunity against short channel effects, inherent capacity of handling low operating voltage, lower leakage current and lower subthreshold swing. However, the problem lies with lower on-state current and ambipolar behaviour of the TFET device which affects its performance. Ambipolarity means the conduction of current in TFET for both positive and negative gate bias. In a conventional TFET, the positive and negative gate voltages reduce the tunnelling barrier width at source/channel and drain/channel interfaces, resulting in increase of current in both the cases. Since the inherent ambipolarity of TFET is undesirable for CMOS logical circuit design, care should be taken to suppress the ambipolar current at negative gate bias. Several techniques like applying low bandgap materials [1], high-k gate oxide [2], dopant engineering, implementation of multi-material gate TFET structures [3], vertical TFETs [4,5] have been utilized over the last few years to enhance on current (I on ). Furthermore, different methods such as employment of high band gap material on the drain side or decreasing the doping concentration of drain region help to mitigate the problem of ambipolar behaviour. But these techniques increase the series resistance of the device, hence deteriorating on-state current. Therefore, a novel technique needs to be evolved which can improve the on current and suppress the ambipolar behaviour of the device. In this study, we propose a work function engineered (WFE) triple metal (TM) gate TFET structure which uses single gate material with different work function values for tunnel gate, control gate and auxiliary gate as shown in Figure 1. Moreover, source and drain region of the device are formed by applying charge plasma concept with suitable work function so that the problem of random dopant fluctuation [6][7][8] and expensive thermal budget [9,10] can be ignored. The choice of work function values for three gate metals and dielectrics of oxide are made in such a way that better on current, lower off current (I off ) and hence better on current to off current ratio are achieved, which matches better with the standard requirements of International Technology Roadmap for Semiconductor (ITRS) [11]. Now the major hindrance lies in complex and difficult manufacturing process of triple work function for gate electrode. In this regard, high-dose nitrogen implantation technique can be helpful to achieve proper integration of triple work functionality of gate material. Molybdenum is used as gate material [12] in our proposed device. To further improve on current, narrow band gap, heterostructures or strained materials can be used. Moreover, Radio frequency (RF) performance of the device has also been investigated and due to its low energy-delay product (EDP), the device can be used for low power RF application. The performance of the proposed structure can easily be realized using commercial 2D numerical device simulator. In our case, the simulation of the device has been carried out in 2D Technology Computer Aided Design (TCAD) Sentaurus. But to get detailed understanding of the device performance in terms of its physical behaviour, an accurate analytical model is needed, which would also be helpful for circuit-level design. The authors in [3] used similar approach of modelling for a TM double gate TFET device in which a parabolic potential distribution is assumed in the channel region. This approximation does not predict correct sinusoids at the semiconductor/oxide interface, thus not giving a good estimate of the device's characteristics length. Hence in this study, we choose evanescent mode of modelling which correctly predicts the device's behaviour in the entire channel region. Moreover, the device performance is also compared with a WFE dual metal TFET device and a conventional TFET device as shown in Figure 1 in order to show how much the performance has been improved. For ease of reference, WFE dual metal TFET device and WFE TM TFET device are renamed as TFET I and TFET II, respectively, in remaining part of this study.
The potential model of the device is derived from Poisson's equation considering the influences of both mobile charge term and depletion charge term. The expression for band to band tunneling (BTBT) generation rates are then obtained using Kane and Kleysh model. By integrating the BTBT generation rate over the entire tunnelling region yields drain current. This mathematical model also predicts the impacts of auxiliary gate work function and control gate work function on surface potential and drain current.
The rest of the study has been organized as follows. Section 2 presents schematic view of the proposed device along with important simulation parameters. A mathematical model is developed in Section 3. Device performance analysis has been discussed with the help of simulation graphs and data in Section 4. Finally, Section 5 concludes the study.

| DEVICE STRUCTURE AND ITS FABRICATION
In this study, WFE dual metal TFET device and WFE TM TFET device are renamed as TFET I and TFET II, respectively. The cross-sectional views of conventional TFET, TFET I and TFET II considered for our study, are shown in Figure 1. In TFET II, high-k dielectric Al 2 O 3 is used as oxide under M1, M2 and comparatively low-k dielectric SiO 2 is used as oxide under M3. The method of using WFE technique together with a suitable gate oxide material in TFET can control the density of carriers in the channel region either making it more n-type or p-type. The use of proper work function value of M3 together with SiO 2 as gate oxide in TFET II prevents to reduce the tunnelling barrier width at drain/channel interface, hence suppressing ambipolarity. The suppression of ambipolarity can be explained from the energy band diagram presented in Figure 2. The energy band diagram of the proposed device under zero bias condition indicates its inherent characteristic of having larger barrier width near drain side, which prevents reduction of tunnelling barrier width on application of negative gate bias. All essential device parameters used for simulation are given in Table 1. For our investigation, we consider L ¼ 30 nm and L ¼ 50 nm. If L ¼ 50 nm is considered, then total length distribution in R2 and R3 of TFET I would be 10 and 40 nm, and length distribution in R2, R3 and R4 of TFET II would be 10, 30 and 10 nm. The depletion regions present near source/channel junction and near drain/channel junction are also taken into account as found in Figure 1. In next section we derive a mathematical model considering these depletion regions as well. The work function of all metals starting from source to drain region in our proposed TM TFET device are chosen to follow this order where φ is the work function of metal. The lower work function for the tunnel gate in case of TM TFET device can reduce the depletion width at source/ channel interface causing more band bending and lowering tunnel barrier width. Hence, on current is improved. On the other hand, use of higher work function in auxiliary gate (as compared to work function value of metal used in drain for charge plasma technique) helps to lower off current or ambipolar current. This TM gate structure with different work functions thus helps to improve switching characteristics and I on /I off ratio more than the method discussed in [13]. Moreover, a Al 2 O 3 layer can be built on Si film using atomic layer deposition (ALD) technique which reduces the chance of trap charges interfering at the Si/Al 2 O 3 interface. This technique of oxide deposition provides excellent integrity and fine controllability on atomic scale thickness [14]. ALD is technique of depositing thin layer of material (oxide or metal) with thickness varying from micrometre to nanometre ranges, on the surface of the semiconductor. The steps that are followed in a single cycle of ALD technique are: ◆ First precursor is exposed in the reactor chamber to form an initial layer on the semiconductor substrate ◆ Evacuation of the excess first precursor and the byproducts ◆ The second precursor is exposed ◆ Removal of the excess second precursor and by-products ◆ The process is continued until the required film thickness is achieved The source region is formed by depositing a suitable source metal (Platinum) with work function 5.93 eV over Al 2 O 3 layer, so that p þ charge carriers can be induced in this region. The drain region is formed by depositing a suitable drain metal (Hafnium) with work function 3.9 eV over Al 2 O 3 layer, so that n À charge carriers can be induced in this region. The thickness of the oxide layer is kept much bigger than 1 nm in order to avoid any gate to channel tunnelling.

| MODEL DEVELOPMENT
For accurate modelling of channel potential, we consider four region (R1, R2, R3, R4) in TFET I and five region (R1, R2, R3, R4, R5) in TFET II including source and drain depletion region for both TFET devices as demonstrated in Figure 1. The region R1 lies under tunnel gate M1 which witnesses the generation of electrons by the process of band-to-band tunnelling. The 2D electrostatic potential in channel region can be solved from 2D Poisson's equation which includes both mobile charge term and depletion charge term as given by the following: where, ψ i ðx; yÞ is the electrostatic potential in i th region of channel, N is doping concentration in the channel, q is the electronic charge and ϵ si is the dielectric constant of silicon, V t is the thermal voltage whose value is 26 mV at 300 K temperature. According to superposition principle, the channel electrostatic potential ψ i ðx; yÞ assumes the following: where, ψ Li ðyÞ being the 1D solution of channel potential in the direction of channel thickness can be determined from: with the following boundary condition ∂ψ Li ðyÞ where, t 0 ¼ t si =2, V FBi is the flat band voltage, C oxi is oxide capacitance per unit area in respective region. The initial solution of ψ Li ðyÞ as obtained following the method reported in [13] is given by the following: Using the initial guess of ψ Li ðyÞ in (1), the final solution of ψ Li ðyÞ is formulated as the following: where, B i can be evaluated by combining (4), (5) and (6) as expressed below: Now, 2D electrostatic potential ψ 2Di ðyÞ can be solved from Laplace equation (using separation of variables method) given by the following: The solution of ψ 2Di ðx; yÞ is expressed as the following: where, λ i is Eigen value and derived from the following: For TM TFET device, the unknown coefficients a i and b i are calculated done with the help of the following boundary conditions pþ source and nþ drain doping concentration of conventional TFET 2 � 10 20 cm À 3 , 5 � 10 18 cm À 3 Abbreviation: TFET, tunnel field-effect transistor.
14 - where, V S and V D are found by V S ¼ À KT q lnð N n i Þ and V D ¼ V ds þ KT q lnð N D n i Þ, N S and N D are the source and drain doping concentration, K is Boltzmann constant. V Ri represents surface potential at the junction of any two regions and can be solved by assuming continuous electric flux and surface potential at the interface of two regions.
The tunnelling length can be defined by the length of tunnelling which starts from the source end and ends where the surface potential in region R2 falls by E G =2, where E G is band gap energy. By this definition, tunnelling length L T can be expressed by the following: where, L d is the Debye length. The average electric field E avg at lower V gs is estimated by the following: and at higher V gs Now substituting E avg into Kane and Kleysh's model for BTBT current [15], the equation for current density can be established as the following: where, A and B are the tunnelling parameters whose default values are 4 � 10 14 V/cm 3 and 2 � 10 7 V/cm, respectively, as used in simulation [15], P ¼ 2:5 for phonon-assisted tunnelling process. In this work, we focus on phonon-assisted tunnelling process, because Silicon is an indirect band gap semiconductor. Now if we ignore band gap narrowing effects, then the factors A and B can be expressed by [16]. and where, m r is the reduced tunnelling mass, h is the Planck's constant, g is the degeneracy factor, m c (m v ) is the effective mass for conduction band (valence band) density of states, ρ is the mass density of silicon, N op indicates the number of transverse optical phonons and given by the following: The transverse acoustic phonon and the transverse optics phonon are the two main contribution of phonon to the tunnelling current. Here, in our study, we consider the transverse optics phonons since the default parameters used in [16] are calibrated with this process.
Formulation of C gg , C gs , and C gd The parasitic capacitances associated with terminal charges of our proposed TFET device can be modelled by following Ward-Dutton method which is used to effectuate the separation of charges into a source charge ðQ s Þ and drain charge ðQ d Þ based on quasi-static condition [17]. The terminal charges Q s and Q d are defined by the following: where, W represents the net effective width of the layer on which the external biases are applied, Q i is the inversion charge density which varies along the channel length. The inversion charge density Q i ðxÞ is simply defined by the following: where, ψ i ðx; t 0 Þ is the position dependent surface potential in respective region. The total charge on the gate terminal is the following: The parasitic capacitances between any two external terminals are then obtained from the following: where, V g , V s and V d are bias applied at gate, source and drain terminals.

| RESULTS AND DISCUSSION
In this section, the performance of the proposed TFET device is analysed with the help of modelled data and TCAD simulation results. In 2D simulation, some important physics models such as concentration dependent model and electric field dependent mobility model, SRH and Auger recombination model, bandgap narrowing model and non-local band-to-band tunnelling models are utilized. Non-local band-to-band tunnelling model is used to include the effect of tunnelling process. As device channel thickness considered in our case is 10 nm, quantum mechanical effects have not been included in this work. The transfer characteristics curves obtained for all the devices as shown in Figure 1 are compared at different bias condition and presented in Figure 3. The similar curves are also obtained considering relatively shorter device length (L ¼ 30 nm) as displayed in Figure 4.
As observed from Figure 3, the simulated drain current value of conventional TFET having L ¼ 50 nm is found to be 6:92 � 10 À 11 Ampere at V ds ¼ 1 V and V gs ¼ 0.5 V which is in consistent with the reported data in [2,18] (also shown in Figure 5), hence the simulation is calibrated. The simulated I on of TFET I and TFET II device are improved by approximately 30 times and 4:3 � 10 3 times, respectively, compared with normal Si TFET at V gs ¼ V ds ¼ 0.5 V. At V gs ¼ V ds ¼ 1 V, the improvement in Ion is found to be approximately 850 times and 14 times, respectively, for TFET II and TFET I device.
The overall improvement in subthreshold slope (SS) as noticed from Figures 3 and 4 is due to having shorter electron tunnelling distance under M1 in both TFET I and TFET II device. The comparative output characteristics obtained from modelled data for TFET I and TFET II devices having L ¼ 50 nm at different bias conditions are also presented in Figure 6.
A list of g m (transconductance), SS and drain induced barrier lowering (DIBL) values as determined from analytical model of TFET I and TFET II devices with L ¼ 50 and 30 nm are tabulated in Table 2. It is found that as L shrinks down, DIBL degrades, but g m of the device increases. In Table 2, SS of 50 nm TFET II is better than 30 nm TFET II. On the other hand, 30 nm TFET I gives better SS than 50 nm TFET I. This improvement in SS can be justified by the measure of I on /I off ratio which is found to be improved in case of 50 nm TFET II and 30 nm TFET I. The improved SS and I on /I off ratio are found to be close to the standard requirements of ITRS [11].
It is pointed out from Figure 6 that drain current in TFET I and TFET II devices attain its saturation earlier than conventional TFET in which saturation is achieved at higher V ds . Figure 7 depicts a comparative DIBL plot of conventional TFET, TFET I and TFET II devices for clear analysis.
The DIBL values are acquired by formulating ∆V th /∆V d from modelled data. Lower DIBL values achieved for TFET II device confirms its better device controllability over the gate. Furthermore, the DIBL values for different L as listed in Table 2 indicate that DIBL can be improved if we consider higher L.
The effects of work function engineering of M1 gate in TFET I and TFET II devices are carefully examined in this section which determines the optimization of the device performance. Figure 8 exhibits transfer characteristics curves of TFET I and TFET II for different work function values of M1. The variation of I on with respect to work function values are also plotted in Figure 9.
It is found from Figure 9 that I on values for TFET II decrease abruptly when work function of M1 (Φ M1 ) exceeds 3.9 eV. But for TFET I, I on values decrease slowly. When Φ M1 is varied from 3.7 to 4.2 eV, the value of Φ M2 and Φ M3 are kept fixed at 4.25 and 4.5 eV, respectively, for device TFET II. It is also observed from Figure 8 that variation of Φ M1 and Φ M2 does not influence SS to vary for both TFET I and TFET II devices. With the reduction of Φ M1 , the lateral tunnelling distance decreases and thus I on increases.
The transconductance values extracted from modelled I d -V gs curve for TFET I and TFET II for V ds ¼ 1 Vis displayed in Table 2. It is also noticed from Figure 10 that peak transconductance for device TFET I and TFET II is occurred at V gs ¼ 0.4 V and V gs ¼ 0.3 V (with g m values are 2.87 � 10 À 6 S/μm and 1.85 � 10 À 4 S/μm, respectively) whereas, for conventional TFET, it happens at V gs ¼ 0.8 V and at comparatively low value (6.79 � 10 À 9 S/μm). The improved peak transconductance is attributed to proper work function engineering of M1 gate in the proposed devices. Moreover, the total gate capacitance (C gg ) along with gate to source capacitance (C gs ) and gate to drain capacitance (C gd ) for all three devices are examined at some fixed bias condition (i.e. V ds ¼ V gs ¼ 0.5 V) and tabulated in Table 3.
The C gg values obtained from model actually gives the summation of C gs and C gd . It is found that at V ds ¼ V gs ¼ 0.5 V, C gg is lowest in TFET I (7.3504 � 10 À 15 F/ μm) which indicates highest cut off frequency for TFET I. Moreover, a device with high cut off frequency (f T ) is deserved to be used for RF application. In this study, the parameters f T and f A (the gain BW product at dc gain of 10) as defined by (23) and (24) are calculated for TFET I and TFET II. Abbreviation: EDP, energy-delay product; TFET, tunnel field-effect transistor.

18
- Due to improved g m and low value of C gg , better f T and f A values are achieved for TFET II at V gs ¼ V ds ¼ 0.5 V. For TFET I, TFET II and conventional TFET, the values of f T and f A are given by 0.36 and 7.24 GHz, 1.39 and 0.28 GHz, 0.69 and 0.14 MHz, respectively.
The EDP of TFET I and TFET II deviceare also investigated which is defined by the product of intrinsic switching energy ðC gg V 2 DD Þ and switching delay ðC gg V DD =I on Þ. Table 4 shows the EDP, intrinsic switching energy (E int ) and the switching delay (t int ) values for TFET I and TFET II at The EDP value found for device TFET II is low because of its higher I on and lower C g . Thus, lower EDP value obtained for TFET II makes it suitable for low power RF application.

| CONCLUSION
In this study, performance of a dual metal TFET device and a TM TFET device (with different channel length values) is analysed based on mathematical modelling and result of numerical simulation. TM TFET device having optimized metal work function values exhibit better dc performance at lowsupply voltage. With the help of calibrated simulation, the device performance has also been compared with conventional TFET. Improvement in device performance has been achieved by application of gate work function engineering technique. TFET I and TFET II with L ¼ 50 nm yields approximately 30 times and 4.3 � 10 3 timesimproved drain current, respectively, at V gs ¼ V ds ¼ 0.5 V, and very small average SS (less than 10 mV/decade) in comparison with conventional TFET device. Moreover, better I on /I off (in order of 10 14 ) is obtained in TFET II device at V gs ¼ V ds ¼ 0.5 V. High f T of 1.39 GHz, high peak g m of 4.26 � 10 À 7 S/μm, low EDP of 24.601 fJ-ns/ μm achieved for TFET II device at V gs ¼ V ds ¼ 0.5 V makes this device suitable for any low-power digital, analogue or RF application.