Soft-switching non-isolated high step-up three-level boost converter using single magnetic element

Abstract

Here, a soft switched three-level boost converter with high voltage gain is proposed which is suitable for high step-up applications with wide output power range. In this converter, a ZVT auxiliary circuit is used which provides soft switching in a wide range of output power independent of load variation. Utilizing coupled-inductors with one magnetic core removes extra auxiliary core in the soft switching circuit and provides high voltage gain in conjunction with size reduction. Also, the secondary and tertiary leakage inductances of the coupled-inductors minimize the reverse recovery problem of the output diodes. Due to its three-level structure, it has very low voltage stress over semiconductor elements in comparison to the existing interleaved structures, resulting in using MOSFETs with low on-resistance and thus lower conduction losses and cost. Operating modes as well as analytical analysis of the proposed converter are discussed. Finally, in order to validate the proposed converter performance, experimental results from a 200-W laboratory prototype are presented.

1 INTRODUCTION

Nowadays, global warming and its impact on environment are turned into a major concern for human beings. Burning fossil fuels to generate energy is known as the main reason for global warming issue. On the other hand, fossil fuel resources are finite, which should be saved for the next generations. Therefore, using renewable energy sources such as photovoltaic (PV) energy is exigent. However, the output voltage of PV panels is relatively low, which cannot satisfy the high voltage DC-link requirements for grid-connected inverters. Connecting several PV panels in series is one solution, which has a number of problems such as module mismatch and shading effect especially for low and medium power applications [1, 2]. The alternative solution is using high step-up DC-DC converters to increase the low output voltage of PV panels. Other applications of high step-up DC–DC converters are fuel cells, batteries, ultra-capacitors used in motor drives, uninterruptible power supplies (UPS), and electric vehicles (EV) [3-5]. A diagram illustrating the usage of high step-up dc-dc converters in renewable-energy-based applications can be observed in Figure 1.

FIGURE 1

Diagram of a grid connected renewable energy system

The conventional boost converter is a basic step-up structure, which cannot be employed in high voltage applications because of its low voltage gain, low efficiency, and high switch voltage stress [4]. One solution to reduce the voltage stress of the boost converter is using a three-level boost structure using two switches. The schematic of the conventional three-level boost converter is presented in Figure 2. The voltage stress is halved over each switch, enabling the usage of MOSFETs with lower drain-to-source on-resistance ($R_{ds(on)}$) and lower conduction loss of the converter. Another two-switch structure based on a boost converter is interleaved boost using two switches and two extra input inductors. In this structure, the input current is divided between switches and thus the current stress of switches is halved [3, 6]. The voltage stress of switches in the interleaved boost structure is two times its three-level counterpart just like the conventional boost converter. The main issue for both three-level boost converter and interleaved boost circuit is that their voltage gain is equal to the conventional boost converter and they still cannot be used for high step-up applications. Additionally, their hard switching operation reduces their usage in high-frequency applications due to high switching loss.

FIGURE 2

Conventional three level boost structure. (a) Hard switching (b) soft switched with ZVT circuit in [10]

To increase the voltage gain of the boost converter and their derivatives, different methods like coupled-inductors and voltage multiplying cells are presented which can prevent converters from operating with high duty cycles [7]. In [8-10], different three-level high step-up boost converters and in [11-15], interleaved high step-up boost structures based on the abovementioned step-up methods are introduced. In [9], a coupled-inductor based three-level converter is introduced, the voltage gain is a bit higher than the conventional three-level and both switches have low voltage stress, however, diode reverse recovery losses considerably degrade the efficiency. Same problems exist in [8] along with using four power switches which degrades the power density and cost. In [11, 12] interleaved high step-up converters using coupled inductors and voltage multiplying cells are introduced. Although in these converters the voltage gain is high, hard switching operation degrades the efficiency.

To improve the efficiency of DC–DC converters and reduce switching losses, different soft-switching methods are introduced including lossless snubbers [17-19], active clamp circuits [20-23], zero voltage/zero current transition (ZVT/ZCT) methods [10, 13–15] and resonant converters [24, 25]. Among these methods, ZVT converters benefit from load-independent soft-switching condition. Likewise, unlike resonant converters, the ZVT converters operate with constant frequency and optimum design of the magnetic components of LC filter is achieved, which is the benefit of pulse width modulation (PWM) converters [24].

In [16-19], interleaved converters employing lossless snubbers are proposed. In the lossless snubbers-based structures, the main switches turn on under ZCS condition, which has high capacitive turn-on loss (E_oss). For the interleaved structure in [16] which uses lossless passive snubber, the voltage gain is increased by diode-capacitor voltage multiplying cells. However, it suffers from reverse recovery losses and a complex structure with the large number of components. In [23, 26], high voltage gain three-level boost converters with active clamp soft switching circuits are proposed. The main limitation of these converters is that they cannot provide soft-switching condition at the wide range of output load. Also, the converter in [26] uses four active switches and a complex control circuit. In [23], an active clamp interleaved converter is proposed which suffers from the high number of components including four power switches and three magnetic cores, plus losing soft switching at light loads.

By using ZVT cells, load-independent soft-switching condition is achieved in [10] for the conventional three-level boost converter (Figure 2) and its conventional interleaved counterpart in [6], which both have a voltage gain equal to the conventional boost converter. In the ZVT interleaved converter in [14], the voltage gain is improved by employing coupled inductors. However, three magnetic cores are required and the structure is complex due to the larger number of elements used. In [15], the presented ZVT interleaved converter employs two coupled inductors and voltage multiplying cells to increase the voltage gain. Nevertheless, the required four power switches and two magnetic cores complicate the structure. In the interleaved topology in [13], two extra ZVT cells are employed which have lots of components including two extra inductors, four capacitors, and two extra switches which results in a high amount of conduction losses and low power density. Note that, the only three-level boost converter which is proposed based on ZVT soft-switching structure is the converter in [10] and as mentioned earlier it has voltage gain equal to the conventional boost converter and cannot be used for high step-up applications. More importantly, the employed ZVT auxiliary cell in this converter has a very high number of components composed of two extra switches, four diodes, and an extra auxiliary magnetic element Figure 2.

Here, a new soft-switching three-level boost converter for high voltage gain applications is proposed, which can provide soft-switching conditions in a wide range of output power, independent of load variations for all semiconductor elements. The three-level structure, which provides converter's switches with low voltage stress, enables using MOSFETs having low $R_{ds(on)}$ and thus low conduction losses. Unlike soft switched three-level converter in [10] and also ZVT interleaved converters in [6, 13–15], the proposed converter uses only one magnetic core by removing the extra core of the resonant inductor in the ZVT cell. This results in reducing the converter size and cost. In this structure, most of the diodes conduct very low current and their losses are not so high to degrade the total efficiency. By providing soft-switching conditions for all semiconductor devices, the reverse recovery and switching losses are alleviated and high efficiency is achieved. Also, the output diode benefits from very low voltage stress which allows using a diode with low reverse recovery and low forward voltage.

Features of the proposed converter can be highlighted as below:

• Very low voltage stress across semiconductor elements
• ZVS soft switching condition for the main and auxiliary switch
• Using coupled inductor and switched capacitor to increase the voltage conversion ratio
• Recycling the leakage inductance energy to the output
• Using only a single magnetic core and reduced size and volume
• Alleviating the reverse recovery losses of the output diodes and efficiency improvement

The paper organization is as follows. In Section 2, the proposed converter topology along with operational principles are discussed. In Section 3, design considerations such as voltage gain expression, selection of elements, and the soft-switching condition are presented. Finally, experimental results of the implemented laboratory prototype and conclusion are provided in Sections 4 and 5, respectively.

2 OPERATING PRINCIPLES OF THE PROPOSED CONVERTER

The circuit diagram of the proposed high step-up three-level boost converter is shown in Figure 3. The proposed converter consists of three active switches S₁, S₂, and S_A, seven diodes D₁ to D₆ and D_A, and four inductors L₁, L_2, L_3, and L_A which are coupled together with one magnetic core. The proposed circuit also has two snubber capacitors C_S1 and C_S2, two passive clamp capacitors C₁ and C₂, two switched capacitors C₃ and C₄, and two output capacitors C_O1 and C_O2. As illustrated in Figure 3, coupled inductors are modelled by a magnetizing inductance L_m and leakage inductances L_lk1, L_lk2, L_lk3, and L_lkA plus an ideal transformer with turns-ratio n₁, n₂, n₃, and n_A. The magnetizing inductance current is assumed to be constant current I_Lm.

FIGURE 3

The proposed soft-switched three-level boost converter. (a) Schematic (b) equivalent circuit

There are sixteen operation modes in one switching cycle; however, since circuit operation for both main switches S₁ and S₂ is symmetrical, only the first eight modes related to S₁ are examined. The key waveforms of the proposed converter are shown in Figure 4 and the equivalent circuit for each operating interval is illustrated in Figure 5. For simplifying the circuit analysis, the following assumptions are made:

FIGURE 4

The key waveforms of the proposed converter

FIGURE 5

Correspondent circuit of the proposed converter associated with switch S

Gating pulses of the main switches S₁ and S₂ are the same as the conventional three-level boost converter with duty cycles > 0.5.

• All the semiconductor devices and passive elements are ideal
• The magnetizing inductance is large enough so its current ripple can be ignored
• The output capacitors C_O1 and C_O2, snubber capacitors C_S1 and C_S2, and the magnetizing inductance L_m are large enough such that their voltage and current ripples can be neglected.
• The output capacitors C_O1 and C_O2 are equal.
• Capacitors C_S1 and C_S2 are equal
• The two leakage inductances L_lk2 and L_lk3 are integrated into L_lk1.

Mode 1 [t₀–t₁] (Figure 5): In this mode, both main switches S₁ and S₂ are conducting and energy is stored in magnetizing inductance of the coupled-inductors. Simultaneously, capacitor C₁ is discharged through diode D₆ and its energy is transferred to C₄. All other diodes plus axillary switch S_A are off and C_O1 and C_O2 supply the output energy. The current equations of the leakage inductance L_lk1 and magnetizing inductance Lm are calculated by:

$$i_{Llk1}\left(t\right)=i_{Llk1}\left(t_0\right)+\frac{V_{in}-\frac{V_{C4}-V_{C1}}{n}}{L_{lk1}}\left(t-t_0\right)$$(1)

$$i_{Lm}\left(t\right)=i_{Lm}\left(t_0\right)+\frac{V_{C4}-V_{C1}}{n.L_m}\left(t-t_0\right)$$(2)

The time duration of this mode is expressed by:

$$\mathrm{\Delta }{t}_1=t_1-t_0=\frac{\left(2D-1\right)T}{2}$$(3)

Where T is the switching period and D is the duty cycle of the main switches S₁ and S₂.

Mode 2 [t₁–t₂] (Figure 5): At t₁, switch S₁ is turned off while switch S₂ and diode D₆ are still conducting. There is a resonance between L_lk1, L_m, and C_S1. Since C_S1 is small, the voltage increment of C_S1 can be considered linear. As a result, S₁ is turned off under zero voltage condition (ZVS). This mode ends when the voltage of C_S1 reaches V_C1. The voltage across C_S1 and time interval of this mode are achieved as:

$$V_{CS1}\left(t\right)=\frac{i_{Llk1}\left(t_1\right)}{C_{S1}}\left(t-t_1\right)$$(4)

$$\mathrm{\Delta }{t}_2=t_2-t_1=\frac{V_{C1}.C_{S1}}{i_{Llk1}\left(t_1\right)}$$(5)

Mode 3 [t₂–t₃] (Figure 5): When the voltage across S₁ reaches V_C1, diode D₁ is turned on and the voltage across S₁ is clamped to V_C1 level. Therefore, the energy of the leakage inductance L_lk1 is absorbed by the clamp capacitor C₁ and voltage spikes across the main switch S₁ are eliminated. Simultaneously, by decreasing the current of leakage inductance L_lk1, diode D₄ starts to conduct and energy of the magnetizing inductance is transferred to the output. The current of L_lk1 decreases linearly and this mode ends when diode D₆ turns off.

$$i_{Llk1}\left(t\right)=i_{Llk1}\left(t_2\right)+\frac{V_{in}-V_{C1}+\frac{n_1}{n_2}{V}_{L2}}{L_{lk1}}\left(t-t_2\right)$$(6)

$$V_{L2}=V_{C1}+V_{C3}-\frac{V_O}{2}$$(7)

$$\mathrm{\Delta }{t}_3=t_3-t_2=\frac{L_{lk1}\left(i_{Lm}-i_{Llk1}\left(t_2\right)\right)}{V_{in}-V_{C1}+\frac{n_1}{n_2}{V}_{L2}}$$(8)

Mode 4 [t₃–t₄] (Figure 5): In this mode, D₆ is off and input energy is transferred to the output. Also, D₁ current reduces linearly to reach zero at t₄. At the end of this, $I_{Lk1}$ reaches $(\frac{n_1}{n_1+n_2})I_{Lm}$.

$$i_{Llk1}\left(t\right)=i_{Llk1}\left(t_3\right)-\frac{\frac{n_1}{n_2}\left(V_{L2}\right)+V_{C1}-V_{in}}{L_{lk1}}\left(t-t_3\right)$$(9)

$$V_{C1}\left(t\right)=V_{C1}\left(t_3\right)+\frac{\left(L_{lk1}+I_{L1}\left(\frac{n_1}{n_2}\right)\right){\mathrm{\Delta }}_{t4}}{C_1}$$(10)

$$\mathrm{\Delta }{t}_4=t_4-t_3=\frac{C_1\left[\frac{V_{in}}{1-D}-V_{C1}\left(t_3\right)\right]}{I_{Llk1}+I_{L1}\left(\frac{n_1}{n_2}\right)}$$(11)

Mode 5 [t₄–t₅] (Figure 5): In this mode, D₁ is off and the input energy is still transferred to the output through D₄. The current of L_lk1 is equal to the secondary side current of coupled inductor L₂ which can be calculated as Equation (9) by using Kirchhoff's Current Law (KCL).

$$i_{Llk1}\left(t\right)=\left(\frac{n_1}{n_1+n_2}\right)I_{Lm}$$(12)

$$\mathrm{\Delta }{t}_5=t_5-t_4=\left(1-D\right)T-\left(\mathrm{\Delta }{t}_4+\mathrm{\Delta }{t}_3+\mathrm{\Delta }{t}_2+t_d\right)$$(13)

In which t_d is the delay between switch S₁ and the auxiliary switch.

Mode 6 [t₅–t₆] (Figure 5): This mode starts when the axillary switch S_A is turned on under ZCS due to the series leakage inductance L_lkA. As the current in the axillary branch increases, the current through D₄ decreases. In this mode, C_S1 voltage is considered almost constant. This mode ends when the current through D₄ reaches zero.

$$n_A{i}_A+n_2{i}_{L2}=n_1\left(I_{Lm}-i_{Llk1}\right)$$(14)

$$i_{Llk1}\left(t\right)=i_{Llk1}\left(t_5\right)+\frac{V_{in}-\left(\frac{1+n_A}{1+n_2}\right)\left(V_X\right)}{L_{lk1}}\left(t-t_5\right)$$(15)

$$i_{LlkA}\left(t\right)=\frac{\frac{V_O}{2}-V_{C3}+\left(\frac{n_2}{n_1}-\frac{n_A}{n_2}\right)\left(\frac{V_X}{1+\frac{n_2}{n_1}}\right)}{L_{lkA}}\left(t-t_5\right)$$(16)

$$\mathrm{\Delta }{t}_6=t_6-t_5=\frac{V_{CS1}.C_{S1}}{i_{LlkA}\left(t_5\right)}$$(17)

In which, $V_X$ is: $V_{in}+V_{C3}-\frac{V_O}{2}$

Mode 7 [t₆–t₇] (Figure 5): In this mode, C_S1 starts to discharge through L_lkA. To simplify the analysis, it is assumed that L_lkA current is almost constant, so the voltage of C_S1 decreases linearly. At the end of this mode, C_S1 reaches zero and D_S1 starts to conduct. The time duration of this mode is:

$$V_{CS1}\left(t\right)=-\frac{i_{Llk1}\left(t_5\right)}{C_{S1}}\left(t-t_6\right)$$(18)

$$\mathrm{\Delta }{t}_7=t_7-t_6=\frac{L_{lkA}.I_{Lm}}{\frac{V_{in}}{1-D}}$$(19)

$$i_{SA}\left(t\right)=i_{SA}\left(t_0\right)-\left(\frac{n{V}_{in}}{L_{lkA}}\right).\left(\frac{L_m}{L_m+L_{lk1}}\right)\left(t-t_7\right)$$(20)

Mode 8 [t₇–t₈] (Figure 4): At the beginning of this mode, S₁ turns on under ZVS condition. In this mode, the axillary switch current i_SA reaches zero. Consequently, switch S_A and diode D_A are turned off under ZCS and the input current flows through S₁ and S₂. As the time duration of mode 8 is too short, it can be neglected.

By the end of this mode, the circuit enters the next eight modes which are complementary with the eight abovementioned modes. In the description of the next eight modes, diodes $D_1,D_4,D_6$ and the switch S₁ should be replaced by $D_2,D_5,D_3$, and switch S₂, respectively and the same operating modes will occur.

3 ANALYSIS OF THE PROPOSED CONVERTER

In this section, design considerations of the proposed converter such as voltage gain, voltage stress of the semiconductor elements, and ZVS range of switches are discussed. Additionally, the performance of the proposed converter is compared with other three-level high step-up converters. Since the duration of modes 2 and 7 are too short in comparison to the other operating modes, these two modes can be neglected.

3.1 Conversion ratio

The proposed converter stores energy in the magnetizing inductance of the coupled inductors and switched capacitors when both main switches S₁ and S₂ are on and then transfers the energy to the output when one of the switches is turned off. Therefore, the operating duty cycle of the converter should be higher than 0.5. Since the circuit is symmetrical, we have:

$$V_C=V_{C1}=V_{C2}$$(21)

$$V_{C3}=V_{C4}$$(22)

$$n=\frac{n_2}{n_1}=\frac{n_3}{n_1}$$(23)

By using the volt-second balance law for L_lk1 and L_m and calculating V_C3 with writing Kirchhoff's Voltage Law (KVL) for mode 8, main equations of the proposed converter are achieved as:

$$K{V}_{in}\left(D-\frac{1}{2}\right)=\left(1-D\right)\left[V_C-\frac{V_A}{n}\right]$$(24)

$$\left(1-K{V}_{in}\right)\left(D-\frac{1}{2}\right)=\left(1-D\right)\left[V_C-\frac{V_A}{n}-V_{in}\right]$$(25)

$$V_{C3}=V_C+nK{V}_{in}$$(26)

In which $V_A$ is: $\frac{V_O}{2}-V_{C3}-V_C$

And K is: $\frac{L_m}{L_m+L_{lk1}}$

After some math works and simplification, the expressions for V_C, V_C3, and voltage gain ($G=\frac{V_o}{V_{in}}$) are as:

$$V_C=\frac{V_{in}}{2\left(1-D\right)}$$(27)

$$V_{C3}=V_{in}\left[\frac{1}{2\left(1-D\right)}+nK\right]$$(28)

$$G=\frac{nK+2}{1-D}$$(29)

As it is seen, the voltage gain provided by Equation (29) is sufficiently high that the proposed converter can be used in high step-up applications even without high turns-ratio of the coupled inductors. Figure 6 shows the voltage gain comparison of the proposed converter with converters presented in [6, 14, 15, 20, 27]. As it is clear, the proposed converter provides higher voltage gain than the other three references in [6, 20, 27] while presenting soft switching performance, low voltage stress and a single magnetic core. Although the proposed converter has a lower voltage gain than the converters in [14, 15], it has lower components in comparison to its counterparts.

FIGURE 6

Voltage gain comparison of the proposed converter with other converters in [6, 14, 15, 20, 27] (n = 1 and k = 1)

Figure 7 illustrates the voltage stress curve of the main switches versus the duty cycle. With n = 1, the voltage stress across the main switches is one-sixth of the output voltage which is very low. In the proposed converter, the voltage stress of the main switches is halved in comparison to converters in [6, 14, 15, 27]. This allows using low voltage power switches with small on-resistance that reduces conduction losses.

FIGURE 7

Voltage stress of the main switch in the proposed converter compared with converters in [6, 14, 15, 27]

In Figure 8 the main switches’ voltage stress is plotted versus the voltage gain, and also it is compared with that of converters in [6, 14, 15, 20, 27]. As can be shown, even in higher voltage conversion ratios, the voltage stress across the power switches of the proposed converter is lower than the compared converters. This lets using low-voltage low-priced MOSFETs with small on-resistance that reduce conduction losses and the overall circuit price.

FIGURE 8

Voltage stress of the switch versus the voltage gain of the proposed converter compared with other converters in [6, 14, 15, 20, 27] (n = 1 and k = 1)

3.2 Voltage stress of the semiconductor elements

As a result of utilizing a passive clamp circuit, the voltage stress of the main switches S₁ and S₂ when one of them is off (mode 3) is equal to V_C, which is using in Equation (27). This voltage stress is sufficiently low and allows us to employ high-quality MOSFETs with lower on-resistance to reduce conduction losses in the circuit.

By considering the circuit in mode 5, the voltage stress of switches S₁ and S₂, as well as diodes D₂ and D₄, is achieved as follows.

$$V_{S1,2}=V_{D2}=V_C=\frac{V_{in}}{2\left(1-D\right)}=\frac{V_O}{2\left(nK+2\right)}$$(30)

Similarly, by doing the KVL and substituting Equation (29) in it, one can calculate the voltage stress of D₄ as:

$$\begin{array}{c}-V_C+V_{D4}+{\displaystyle \frac{V_O}{2}}=0\hfill \\ V_{D4}={\displaystyle \frac{V_{in}\left(nK+1\right)}{2\left(1-D\right)}}={\displaystyle \frac{V_O\left(nK+1\right)}{2\left(nK+2\right)}}\hfill \end{array}$$(31)

Since the circuit is symmetrical, the voltage stress of diodes D₁ and D₅ are the same as Equations (30) and (31) respectively.

Considering mode 4, the voltage stress of diodes D₃ and D₆ are the same and equal to:

$$V_{D3}=V_{D6}=\frac{V_O}{2}-\frac{V_{in}}{2\left(1-D\right)}$$(32)

For the axillary switch S_A, we have:

$$V_{SA}=\frac{V_O\left(n_A-1+2D\right)}{2\left(nK+2\right)n_A}$$(33)

3.3 Design of magnetic inductance

The magnetizing inductance can be calculated as below.

The voltage across L_m is:

$$V=L\frac{\mathrm{\Delta }I}{\mathrm{\Delta }t}$$(34)

In which the conduction time is:

$$ton=\frac{\left(2D-1\right)}{2}T$$(35)

V_in is applied across L_m, so:

$$L=\frac{V_{in}\ast \left(2D-1\right)}{2\mathrm{\Delta }I.f}$$(36)

Therefore, $V_C=V_{C1}=V_{C2}=\frac{1}{2(1-D)}{V}_{in}$, the above equation can be rearranged as below:

$$L=\frac{(V_{in-Vc2)}\ast \left(1-D\right)}{2\mathrm{\Delta }I.f}$$(37)

3.4 Design of capacitors

In this section, the design equations for the capacitors are provided. The output capacitors, clamp capacitors and the multiplier capacitors can be designed by considering the desired ripple voltage as following.

$$C_{o1}=C_{o2}=\frac{\left(D-\frac{1}{2}\right)I_o}{f\ast \mathrm{\Delta }{V}_o}$$(38)

$$C_1=C_2=\frac{\mathrm{\Delta }{t}_4(I_{Lm}+\left(n+1\right)I_{L2})}{f\left(n+1\right)\ast \mathrm{\Delta }{V}_o}$$(39)

$$C_3=C_4=\frac{\left(1-D\right)I_{Lm}}{f\left(n+1\right)\ast \mathrm{\Delta }{V}_o}$$(40)

Where $\mathrm{\Delta }{t}_4$ is achieved by Equation (11). Also, the snubber capacitors are obtained by Equation (41).

$$C_{s1},C_{s2}>\frac{i_{sw}\ast t_f}{2V_{sw}}$$(41)

Where V_sw, i_sw, t_r, and t_f are the maximum switch voltage and current and the switch current rise and fall times, respectively.

3.5 Performance comparison

The proposed converter is compared with other high step-up counterparts and the results are reported in Table 1. Converters in [8, 9] need only one magnetic core and have the lowest component count. However, they suffer from higher switch voltage stress, severe reverse recovery losses, and hard switching performance. The active clamp converters in [20-23] are load-dependent and cannot provide soft-switching condition at specific light loads. Also, although the converter in [20] has a low number of diodes and use only one magnetic core, it suffers from low voltage gain, high switch voltage stress, and does not provide soft-switching condition at light loads. As can be seen, most of the compared converters utilize more than one magnetic core, especially converters in [6, 14–16, 18, 21, 22] that need three or more. In contrast, the proposed converter employs only one magnetic element, which is an important feature for the proposed converter. From the component count point of view, the proposed converter needs relatively fewer elements, however, converters [14, 15, 18] utilize a large number of components and have a complex structure. Also, converters [6, 10, 20] are made up of fewer elements, but their voltage gain is low, and [6] suffers from a very high switch voltage stress and reverse recovery losses. Looking at the switch voltage stress, it can be seen that the proposed converter endures the lowest voltage stress across its switches, while, converters [6, 8, 9, 13, 16] face a considerably high switch voltage stress. With a closer look at [10], though it has a fewer number of elements and a switch voltage stress equal to the proposed converter, it requires two magnetic cores, has a very low voltage gain, and suffers from reverse recovery losses. In terms of the converter cost, it can be observed that the proposed converter is cheaper than its counterparts. Although the converters in [10, 20–22] are cheaper than the proposed converter, they all have a lower voltage gain than the proposed converter. In addition, the converters in [20-22] endure a higher voltage stress across their power switches and the reverse recovery losses is major in [21]. It should be mentioned that the power switches, especially the high-voltage ones, are of the pricier elements in power converters, hence, converters with higher number of power switches are usually more expensive, as can be seen in [8, 13, 23]. In terms of the input current, the ZVT converters in [13-15] as well as the proposed converter have discontinued input current unlike the converters in [6, 10] which increases the size of the input filter. Although converters in [6, 10] benefit from continues input current, their voltage gain is equal to the boost converter. To sum up, although some counterparts have higher voltage gain or fewer elements, the proposed converter has established a reasonable compromise between the desired parameters. Using only one magnetic core, a simple soft-switching scheme with the least number of components, a wide range of soft-switching performance, ultra-low switch voltage stress, reduced reverse recovery losses, and high voltage gain are the remarkable advantages of the proposed converter. More importantly, because of the three-level structure and minimized voltage stress across the circuit elements, low-priced low-voltage power switches, diodes, and capacitors are employed in the proposed converter which makes it a cost-effective option for high voltage gain applications. Also, reducing the number of power switches, magnetic cores, and windings helps to cut the price and size. The proposed converter is amongst the ones that use the highest number of diodes, but it should be noted that only two of these diodes, D₄ and D₅, are in the main power path. In addition, compared with power switches, the cost of diodes is much cheaper because the average current of diodes is very low. All these advantages make the proposed converter a suitable option for applications that need a high voltage conversion ratio and high efficiency like PV panels and fuel cells.

TABLE 1. Comparison of the proposed converter with other high step-up DC–DC converters

					Number of components
Topology	Soft switching cell	Voltage gain	Switch voltage stress	Voltage stress (n = 1, D = 0.7, VO = 400)	MOS*	D*	Cap*	Win*	Core	Total	VDO/$V_o$	Input current	No R.R*	Cost ($)
Ref. [8]	Hard switching	$\frac{1}{1-D_1+D_2}$	$\frac{V_o}{2}$	200	4	8	2	1	1	16	1	C*	✗	39.41
Ref. [9]		$\frac{2(1+nD)}{1-D}$	$\frac{V_o}{2}$	200	2	4	2	2	1	11	$\frac{1}{2}$	D*	✗	36.24
PCWZ*		$\frac{2+n}{1-D}$	$\frac{V_o}{2(n+2)}$	66.6	2	6	6	3	1	18	$\frac{1}{2}$	D	✓	15.84
Ref. [16]	Lossless Snubber-ZCS (on) (LI*)	$\frac{2{n_m}^1}{(1-D)}$	$\frac{V_o}{2n_m}$	200 $n_m$	2	$5+2n_m$	$2+2n_m$	4	4	11+4$n_m$	—	C	✗	26.84
Ref. [17]		$\frac{2n+2}{1-D}$	$\frac{V_o}{2n+2}$	100	2	8	5	6	2	23	$\frac{1}{2}$	D	✓	28.08
Ref. [18]		$\frac{2n_2(1+n_1)+1}{3n_2(1+n_1)+2}$	$\frac{V_o}{3n_2(1+n_1)+2}$	–	2	8	7	7	3	27	$\frac{2n_2(1+n_1)+1}{(1+n_1)+2}$	D	✓	39
Ref. [19]		$\frac{2+nD}{1-D}$	$\frac{V_o}{2+nD}$	148	2	8	5	4	2	21	1	D	✗	28.84
Ref. [20]	Active clamp (LD*)	$\frac{1+n}{1-D}$	$\frac{V_o}{2(1+n)}$	100	3	4	8	3	1	19	$\frac{1}{2}$	D	✓	17.73
Ref. [21]		$\frac{n(1+D)}{1-D}$	$\frac{V_o}{n(1+D)}$	235	3	7	7	5	3	25	$\frac{1}{2}$	D	✗	17.62
Ref. [22]		$\frac{2}{1-D}$	$V_o$	400	3	6	4	4	4	23	1	C	✓	18.14
Ref. [23]		$\frac{2(n+1)}{1-D}$	$\frac{V_o}{2(1+n)}$	80	4	4	5	5	3	21	1	C	✓	37.64
Ref. [6]	ZVT (LI*)	$\frac{1}{1-D}$	$V_o-V_{Ca}$	390	3	4	4	4	3	18	1	C	✗	28
Ref. [10]		$\frac{1}{1-D}$	$\frac{V_o}{2(n+2)}$	66.6	4	6	2	2	2	14	$\frac{1}{2}$	C	✗	14.5
Ref. [13]		$\frac{2n+1}{1-D}$	$V_o$	400	4	8	7	4	2	25	$(1+\frac{2(1-D)}{2n+1})$	D	✗	42.31
Ref. [14]		$\frac{1+3n}{(1-D)}$	$\frac{V_o}{1+3n}$	100	3	10	6	8	3	30	—	D	✓	29.31
Ref. [15]		$\frac{2(1+n)}{1-D}$	$\frac{V_o}{2(1+n)}$	100	4	6	7	8	4	29	$\frac{(1+2n)}{2(1+n)}$	D	✓	36.5
Proposed		$\frac{2+n}{1-D}$	$\frac{V_o}{2(n+2)}$	66.6	3	7	6	4	1	21	$\frac{1}{2}$	D	✓	20.29

• MOS, MOSFET; D, Diode; Cap, Capacitor; Win, Winding, LD, Load-dependent, LI, Load-independent, RR, Reverse recovery, C, Continuous, D, Discontinuous, PCWZ*, Proposed converter without ZVT.

3.6 Control circuit performance

The control circuit which is shown in Figure 12 is composed of four main sections. The first section is a feedback isolator which is implemented by isolating the output voltage via TL431 and an optocoupler. The second one is a pulse width modulation (PWM) controller that adjusts the duty cycle according to the output voltage based on traditional voltage control. This stage is implemented using a PWM controller (SG3527 IC) and produces two pulses with 180 degrees phase shift. The fourth stage is a monostable IC with the pulse delay circuit to produce the gate-source voltage of the auxiliary switch with the desired duty cycle and delay. According to the operating principles, before turning each of the main switches on, the auxiliary switch should be turned on with an appropriate time delay and duty cycle. The gate-source voltage of the switches is applied by a gate-driver circuit with isolation and amplification.

4 EXPERIMENTAL RESULTS

To validate the performance of the proposed converter, a laboratory prototype with input voltage 40 V, the output voltage of 400 V, and rated power 200 W has been implemented. Figure 9 and Table 2 provide the photograph and important parameters of the implemented prototype, respectively. Experimental results of the proposed converter are illustrated in Figure 10. Current and voltage waveforms of the main and auxiliary switches in light load are shown in Figure 11b. As can be seen in Figure 10, the drain-source voltage of S₁ is about 70 V which is less than a quarter of the output voltage. It allows choosing low-voltage switches with small on-resistance that leads to efficiency improvement. Moreover, at the turn-on instant of S₁, the switch current i_ds1 is negative which shows ZVS performance of S₁ that removes switching losses. Also, ZVS turn-off of S₁ can be observed which is due to Cs₁. S₂ has an identical condition as S₁. As shown in Figure 10, the maximum voltage across S_a is about 90 V which is much lower than the 400 V output voltage. Besides, as it is observed in Figure 10, S_a turns on under ZCS because of the series leakage inductance and turns off under ZVZCS condition. The voltage and current waveforms of D₁ is shown in Figure 10. The maximum reverse voltage across D₁ is about 120 V. As can be seen through i_D1, D₁ turns on and off under ZCS condition. In Figure 10, the maximum voltage across D₃ is about 50 V which is much lower than the output voltage. The ZCS turn-on and turn-off performance of D₃ can be observed in this figure. The current and voltage waveforms of D₄ can be observed in Figure 10. The maximum voltage across D₄ is about 140 V and D₄ turns on and off in a ZCS manner. As it is observed, all diodes endure low voltage stress and have ZCS turn-off performance. These two factors both help decrease their associated reverse recovery losses dramatically and improve efficiency. The low voltage stress across diodes also makes it able to choose low-voltage high-quality diodes with lower recovery times. As illustrated, not only the voltage stress of the switches is limited, but also their operation is under zero voltage condition. To show the soft-switching operation of the converter at light loads, the voltage and current of switches at 40 W output power are illustrated in Figure 11. Just like the full-load condition, the soft-switching is achieved for all switches at light loads. Since the operation of switch S₂ is the same as S₁, it is not shown in the figures.

FIGURE 9

Prototype of the implemented circuit

TABLE 2. Parameters of the implemented prototype

Parameter	value
Input voltage Vin	40 V
Output voltage Vo	400 V
Output power Po	200 W
Switching frequency fs	50 kHz
Main switches S1 and S2	IRF3710
Auxiliary switch SA	IRF3710
Diodes D1, D2, D3, D6 and DA	BYV32
Diodes D4 and D5	MUR460
Magnetizing inductance Lm	200 μH
Primary-side leakage inductance Llk1	3 μH
Turns ratios of n2/n1 and n3/n1	1
Turns ratios of nA/n1	0.4
Clamp capacitors C1 and C2	4.7 μF/100 V
Snubber capacitors Cs1 and Cs2	2 nF/100 V
Switched capacitors C3 and C4	4.7 μF/250 V
Output capacitors CO1 and CO2	22 μF/250 V

FIGURE 10

Experimental waveforms of the implemented prototype at full load. (a) Main switch S₁ (b) auxiliary switch $S_a$ (c) diode D₁ (d) diode D₄ (e) diode D₆

FIGURE 11

Experimental waveforms of the switches at light loads. (a) Main switch S₁ (b) auxiliary switch $S_a$

FIGURE 12

Experimental Control circuit of the proposed converter

The circuit components are analysed separately in terms of power loss at both full load and light load (%20 of the nominal load) condition for the proposed converter and converters in [14, 15] (Figure 13). Only the important components including the power switches, diodes, and inductors are considered and the rest of the losses associated with the gate driver and capacitors are aggregated in the chart bar named “Others”. A-Diodes for the proposed converter stands for Auxiliary diodes which are D₁, D₂, D₃, D₆, and D_A, and M-Diodes denote the main diodes which are D₄ and D₅. As Figure 13 shows, the conduction losses of the main switches and diodes have the highest share of total losses. Besides, though there are seven diodes used in the proposed converter, only two of them, D₄, and D₅, are within the main power path, and as the chart shows, the total power dissipations of all the auxiliary diodes are a little higher than the main diodes. The main advantage of the proposed converter is that the voltage stress of the switches is half of the other converters in [14, 15], which results in lower conduction losses and higher total efficiency. In Table 3 the conduction losses of components in the nominal load are calculated. As expected, the conduction losses of the main switches are dominant, and apart from the main switches, more power is dissipated by the main diodes D₄ and D₅ than the other elements. It should also be noted that the reason for the difference between S_A loss values reported in Figure 13 and Table 3 is that E_oss loss associated with S_A is not calculated in Table 3 and it is included in power loss analysis reported in Figure 13.

FIGURE 13

Loss distribution of the proposed converter in comparison with converters in [14, 15] at full-load (first rows) and light-load (second rows)

TABLE 3. Conduction losses of the components used in the proposed converter

Component	Resistance [Ω]	RMS current [A]	Power loss [W]
Main switches S1,2	0.023	6.44	2×0.95
Auxiliary switch SA	0.023	1.29	0.038
Inductor LA	0.01	1.29	0.016
Inductor L1	0.012	5.6	0.37
Inductors L2 and L3	0.024	1.38	2×0.045
Component	Voltage drop [V]	Average current [A]	Power loss [W]
Diode D1,2	0.71	0.5	2×0.35
Diode D3,6	0.71	0.5	2×0.35
Diode D4,5	0.71	0.5	2×0.35
Diode DA	0.71	0.3	0.21
Total			4.7

The efficiency of the proposed converter shown in Figure 14 is achieved using PSpice simulation software along with the experimental measurement and is compared to some of its counterparts. Note that, IRF3710 ($V_{DS}=$100 V, $R_{ds(on)}$= 23 mΩ) is utilized for the main and the auxiliary switch of the proposed converter. Also, for switches of converters in [14, 15], IRL640A ($V_{DS}=$200 V, $R_{ds(on)}$= 180 mΩ) is used, due to having higher voltage stress. The results are illustrated in Figure 14. As can be seen the proposed converter has the highest full-load efficiency which is %97.4 for the simulation and %97.2 for the experimental measurement at 200 W output power. In addition, there is no considerable efficiency drop at light loads thanks to its ZVT soft-switching circuit, which are %97 and %96.5 for the simulation and experimental measurements, respectively. Although the converter presented in [14] has also a high efficiency at a wide range of output loads, its efficiency is lower than the proposed converter at full loads due to higher conduction loss of the main switches and large number of semiconductor elements. The converter in [15] not only have a remarkably lower full-load efficiency but also its efficiency dramatically drops at light loads. Another disadvantage of the converter in [15] is that it needs two auxiliary power MOSFET to achieve soft switching which more degrades the efficiency.

FIGURE 14

Efficiency of the proposed converter in comparison with other converters in [14, 15]

5 CONCLUSION

Here, a new single-core soft-switching high step-up three-level converter with a passive clamp circuit was introduced. All semiconductor elements have soft switching performance. The voltage stress across the main switches S₁ and S₂ along with the auxiliary switch S_A is less than a quarter of 400 V output voltage. The proposed circuit topology is suitable for high step-up applications and has some advantages such as reduced size because of using only one magnetic core, high efficiency as a result of utilizing soft-switching techniques, low voltage stresses across the semiconductor elements, absorption and recycling of leakage inductance energy, and low conduction loss since three-level structure enables using MOSFETs with low drain-to-source on-resistance. The coupled inductors and switched capacitors are integrated to achieve high step-up voltage gain. The secondary and tertiary leakage inductances of the coupled inductors also reduce the reverse recovery problem of the output diodes which improves the circuit performance.

CONFLICT OF INTEREST

The authors declare no conflict of interest.

Open Research

DATA AVAILABILITY STATEMENT

The data that support the findings of this study are available from the corresponding author upon reasonable request.