49.35 MHz GBW and 33.43 MHz GBW amplifiers in flexible a-IGZO TFT technology
Abstract
The authors present the implementation of two amplifiers in a commercial flexible amorphous Indium Gallium Zinc Oxide (a-IGZO) thin-film transistor (TFT) technology: a Cherry Hooper (CH) amplifier and a 4-stage common source amplifier. The CH amplifier is designed as a pre-amplifier for wireless receivers. It is optimised for a high gain-bandwidth product (GBW). From a supply voltage of V it provides 19.4 dB gain and has a
-bandwidth of 5.3 MHz, while consuming 0.2 mW. It has a GBW of 49.35 MHz, which is more than a factor two better than previously reported a-IGZO TFT amplifiers. The 4-stage common source amplifier is designed as output buffer, has a very wide range of operating conditions and strong robustness against manufacturing tolerances. From a supply voltage of
V it provides 28.9 dB gain, has a
-bandwidth of 1.2 MHz, and a GBW product of 33.43 MHz, while consuming 14.2 mW. Both circuits can operate from a supply voltage between 2.5 and 10 V.
Introduction
Flexible electronics is widely expected to enable new wearable, Internet of things, and health care applications, because they integrate into our daily life and environment much better than rigid electronics [1]. High-gain high-frequency amplifiers will be key building blocks for these new applications. An important semiconductor for flexible electronics is amorphous Indium Gallium Zinc Oxide (a-IGZO), as it can have effective carrier mobilities in the range of 15–50 cm/Vs2 [2], which is high for flexible technology. The recent technological advances in flexible a-IGZO thin-film transistors (TFTs) enable a great leap forward towards flexible wireless communication systems at 13.56 MHz. In this work, we demonstrate for the first time, a flexible a-IGZO amplifier that provides significant gain at 13.56 MHz, which is an important free ISM band for short range wireless communication systems including NFC- and RFID-systems.
A-IGZO TFT technology
The 0.8 technology of PragmatIC®, with n-type metal oxide transistors based on a-IGZO, was implemented in this work. Circuits are manufactured on a sub-15
polyimide substrate using PragmatIC's fab-in-a-box manufacturing line, FlexLogIC® [3]. To enable the use of industry standard tooling and allow sub-micron feature sizes to be achieved, the polyimide substrate is spin-coated onto a glass carrier wafer before processing commences. After manufacture, the polyimide substrate can be diced and circuits released from the glass for assembly into inlays, for example. The glass is subsequently recycled. Transistor, resistor and tracking layers are built up using repeated sequences of material deposition, patterning and etching, with typical transistor geometries of 5/0.8
(channel width/channel length) and resistor values of 3 M
. A total of 13 layers are used in circuit manufacture, which includes 4 layers of routable metals. A photolithographic stepper tool is used for feature patterning, which images a shot that is repeated at multiple instances across the 200 mm wafer for the definition of each patterned layer. These device dimensions represent the current process node of the technology rather than the fundamental limits of the tooling. Table 1 shows key transistor metrics. All circuit simulations are done with Berkeley's threshold-voltage based BSIM4 transistor model [4], which has been fitted to the TFT characteristics.

Parameter | Typical values |
---|---|
VTH | 0.43 V |
subthreshold slope | 100 mV/dec |
ION (lin.) | 1.77 ![]() |
ION (sat.) | 31.4 ![]() |
Hysteresis | 60 mV |
Cherry-Hooper amplifier
A Cherry-Hooper (CH) amplifier (T1, T2, and T3 in Fig. 1), in general, is a two stage common source (CS) amplifier with positive feedback from the second to the first CS stage. It achieves high gain-bandwidth (GBW) products [5]. We optimised the presented CH implementation for maximum bandwidth, and thus for the amplification of RF input signals in flexible wireless systems. Its input can, for example, be directly connected to a receiving antenna of an NFC system. To decouple the amplifier characteristics from subsequent circuitry we include a source follower (SF) buffer (TSF in Fig. 1). Since output vOUT will connect to integrated circuitry, the SF buffer has a small driving capability ( @10 MHz). Consequently, the electrical characterisation of the CH requires the use of an active probe tip, which loads the circuit with only 50 fF
1.25 M
. Even this probe is a much heavier load than a transistor gate. Consequently, the amplifier will perform even better in an actual integrated circuit than the presented measurement results indicate. The CH amplifier schematic is shown in Fig. 1. The measurements, as well as their comparison to simulation, are shown in Fig. 2. The measured linearity @1 MHz is shown in Fig. 3.

Schematic diagram of CH amplifier, including measurement setup

Measured (dots) and simulated (line) magnitude (orange) and phase (blue) of the voltage gain Av
v
of the CH amplifier. Measured voltage gain (green) of the presented 4-stage CS amplifier is shown for comparison

Measured 1 dB compression points @1 MHz of CH amplifier (orange squares) and 4-stage CS amplifier (green triangles)
4-stage common source amplifier
The presented CS amplifier is a 4-stage implementation with all ac-coupling (Fig. 4). The biasing scheme via feedback resistors RBx enables a very wide supply voltage range and strong robustness against manufacturing tolerances. We optimised this amplifier to have a strong driving capability as well as a large bandwidth. As measure for driving capability we use the output impedance, which for the presented device dimensions is @10 MHz. We use the CS amplifier as output buffer of larger designs for direct characterisation with a long cable and an oscilloscope (14 pF
1 M
). For this application, its robustness, wide supply voltage range, and high input impedance are very important. The high input impedance (
k
@10 MHz) of the amplifier minimises its load on any internal circuit nodes that serve as signal input. The CS amplifier schematic is shown in Fig. 4. The measurements as well as their comparison to simulation are shown in Fig. 5. The measured linearity @1 MHz is shown in Fig. 3.

Schematic diagram of CS amplifier, including measurement setup

Measured (dots) and simulated (line) magnitude (orange) and phase (blue) of the voltage gain Au
u
of 4-stage CS amplifier. Measured voltage gain (orange) of the presented CH amplifier is shown for comparison
Conclusion
Fig. 6 shows the die micrographs of the CH and the 4-stage CS amplifier. The dimensions of the amplifier cores are 500 m
520
and 770
m
425
, respectively. Table 2 summarises the measurement results of the CH and CS amplifier, and compares them to the state-of-art of a-IGZO TFT amplifier circuits. For reference, we also include an amorphous Silicon (a-Si) TFT amplifier and a low-temperature poly-Si oxide (LTPO) CMOS amplifier. The amplifiers presented in this work significantly outperform previous flexible a-IGZO TFT amplifiers in terms of bandwidth BW, gain-bandwidth product GBW, unity-gain frequency fUG, power consumption P, as well as area. The CH amplifier was designed as pre-amplifier, the CS amplifier as a buffer. The presented CH amplifier is the first flexible a-IGZO amplifier that provides a significant gain in the 13.56 MHz free ISM band. Based on this circuit, we are now for the first time able, to considerably increase the input sensitivity of a-IGZO TFT wireless systems that operate in the 13.56 MHz ISM band, which includes NFC- and RFID-applications.

Die micrographs of the
a CH amplifier and
b 4-stage CS amplifier
Ref. | ![]() ![]() |
Top. | ![]() |
![]() |
BW in MHz | GBW in MHz | ![]() |
P in mW | A in ![]() |
---|---|---|---|---|---|---|---|---|---|
Thiswork | 0.8 | CH | 8 | 19.4 | 5.3 | 49.35 | 30.00 | 0.19 | 0.3 |
0.8 | CS | 8 | 28.9 | 1.2 | 33.43 | 11.50 | 14.24 | 0.3 | |
[8]* | 10 | OP | 15 | 29.5 | 0.01 | 0.28 | 0.18 | 5.00 | 1 |
[9]* | 2 | OP | ![]() |
23.5 | 0.5 | 7.50 | 2.37 | 51.00 | 0.7 |
[10] | 20 | OP | 10 | 10.0 | 0.1 | 0.20 | 0.20 | ![]() |
1.1 |
[11] | 10 | OP | 13 | 24.9 | 0.01 | 0.09 | — | 1.30 | 11.2 |
[12] | 15 | OP | 10 | 22.0 | ![]() |
0.04 | — | 0.03 | 52.5 |
[13] | 4 | CH | 6 | 9.5 | 2.4 | 7.16 | 4.10 | 6.00 | 13.3 |
[14] | 15 | OP | ![]() |
14.0 | ![]() |
0.01 | ![]() |
50.00 | 0.8 |
[14] | 15 | OP | ![]() |
21.5 | ![]() |
0.01 | ![]() |
2.00 | 0.8 |
[14] | 15 | OP | ![]() |
30.0 | ![]() |
0.01 | 0.01 | 0.40 | 0.8 |
[15]* | 10 | OP | ![]() |
24.5 | 0.01 | 0.10 | — | — | 1.3 |
[16] | 5 | OP | 6 | 19.0 | 0.03 | 0.22 | 0.33 | 6.80 | 25.2 |
[17] | 4 | CS | 6 | 17.0 | 0.1 | 0.56 | 0.70 | 0.80 | 7.5 |
[17] | 4 | CA | 6 | 25.0 | 0.2 | 3.91 | 3.00 | 2.30 | 10.3 |
[18] | 3 | CH | 6 | 10.4 | 3.5 | 11.59 | — | 1.50 | 9.7 |
[18] | 6 | CH | 6 | 33.3 | 0.4 | 18.50 | — | 4.70 | 15.1 |
[19] | 5 | OP | 5 | 22.5 | 0.01 | 0.08 | 0.03 | 0.20 | 9.8 |
[20] | 6 | OP | 5 | 18.7 | 0.1 | 0.93 | 0.47 | 0.90 | 2.1 |
[21] | 3.6 | CA | 6 | 10.0 | 2.9 | 9.17 | 7.00 | — | 7.6 |
[21] | 10 | CS | 6 | 10.0 | 0.8 | 2.37 | 2.00 | — | 11.6 |
[22] | 2.5 | CA | 5 | 7.8 | 0.8 | 2.06 | 1.30 | 0.40 | 0.8 |
[22] | 2.5 | CS | 5 | 6.8 | 1.2 | 2.63 | 2.80 | 0.70 | 0.8 |
[6]* LTPO CMOS | 6 | OP | ![]() |
50.7 | 0.2 | 68.55 | 7 | 0.60 | 0.1 |
[7]* a-Si | 8 | OP | 25 | 42.5 | ![]() |
0.27 | 0.03 | 3.50 | — |
Acknowledgments
This work was supported in part by the DFG under projects WISDOM II and Coordination Funds 2 of SPP 1796 under grants nos. 271795180 and 270774198, in part by the European Regional Development Fund (EFRE), and in part by the Free State of Saxony.